SRAM_CTRL/RET Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.570s	101.573us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.790s	28.553us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	86.000us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.950s	46.688us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.780s	15.876us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.860s	107.111us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	86.000us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	15.876us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.940s	456.571us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.090s	177.175us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.231m	11.873ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.032m	7.269ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	30.000s	9.599ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.407m	868.646us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.240s	939.559us	1	1	100.00
V2	executable	sram_ctrl_executable	12.874m	117.621ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.030s	298.607us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.211m	37.029ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	12.090s	322.113us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.260s	198.417us	1	1	100.00
		sram_ctrl_throughput_w_readback	42.120s	300.819us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.484m	14.929ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.140s	34.231us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	51.008m	220.644ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.570s	29.527us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.990s	69.288us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.990s	69.288us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.790s	28.553us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	86.000us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	15.876us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.490s	50.105us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.790s	28.553us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	86.000us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	15.876us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.490s	50.105us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.480s	5.667ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.030s	4.196us	0	1	0.00
		sram_ctrl_tl_intg_err	3.240s	648.576us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.030s	4.196us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.240s	648.576us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.484m	14.929ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.484m	14.929ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	86.000us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.874m	117.621ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.874m	117.621ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.874m	117.621ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.240s	939.559us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.620s	93.894us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.480s	5.667ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.050s	438.278us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.570s	101.573us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.570s	101.573us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.874m	117.621ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.030s	4.196us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.240s	939.559us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.030s	4.196us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.030s	4.196us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.570s	101.573us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.030s	4.196us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	45.150s	2.668ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.97028323037127702980534696890978166016358365872442039344498711776041002227128
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4196263 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4196263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---