SYSRST_CTRL Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: `5c5f5a8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.890s	2.133ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	6.550s	2.460ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.720s	2.212ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.100s	2.325ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.680s	4.053ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.750s	2.062ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.590m	75.304ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.930s	2.081ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	3.190s	2.102ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.750s	2.062ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.930s	2.081ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	39.010s	60.588ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	44.970s	94.359ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	4.100s	3.762ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	11.630s	5.544ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	6.530s	2.512ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.920s	2.230ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	6.640s	4.729ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	6.690s	2.610ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.350s	9.506ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	33.580s	42.597ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	5.510s	8.114ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	5.320s	2.013ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.780s	2.025ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	6.680s	2.057ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	6.680s	2.057ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.680s	4.053ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.750s	2.062ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.930s	2.081ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.090s	4.975ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.680s	4.053ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.750s	2.062ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.930s	2.081ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.090s	4.975ms	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	25.310s	22.032ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	47.430s	22.236ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	47.430s	22.236ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.730s	4.042ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*])

has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

0.sysrst_ctrl_stress_all_with_rand_reset.20955207359885107946552221095813391501850021723723063663212468103021912804755
Line 384, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4041748102 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 4041748102 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4041748102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---