UART Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	14.240s	5.722ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.590s	29.502us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.660s	12.987us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.010s	176.388us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.530s	39.102us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.800s	75.239us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.660s	12.987us	1	1	100.00
		uart_csr_aliasing	1.530s	39.102us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	14.710s	48.087ms	1	1	100.00
V2	parity	uart_smoke	14.240s	5.722ms	1	1	100.00
		uart_tx_rx	14.710s	48.087ms	1	1	100.00
V2	parity_error	uart_intr	2.819m	477.870ms	1	1	100.00
		uart_rx_parity_err	12.130s	37.303ms	1	1	100.00
V2	watermark	uart_tx_rx	14.710s	48.087ms	1	1	100.00
		uart_intr	2.819m	477.870ms	1	1	100.00
V2	fifo_full	uart_fifo_full	10.410s	15.200ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	49.950s	129.446ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.539m	94.188ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.819m	477.870ms	1	1	100.00
V2	rx_break_err	uart_intr	2.819m	477.870ms	1	1	100.00
V2	rx_timeout	uart_intr	2.819m	477.870ms	1	1	100.00
V2	perf	uart_perf	13.762m	21.375ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.850s	910.880us	1	1	100.00
V2	line_loopback	uart_loopback	2.850s	910.880us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	6.210s	12.457ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.310s	4.563ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.680s	5.121ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	10.250s	6.951ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.664m	90.856ms	1	1	100.00
V2	stress_all	uart_stress_all	2.435m	153.232ms	1	1	100.00
V2	alert_test	uart_alert_test	1.530s	17.309us	1	1	100.00
V2	intr_test	uart_intr_test	1.400s	35.819us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.660s	210.724us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.660s	210.724us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.590s	29.502us	1	1	100.00
		uart_csr_rw	1.660s	12.987us	1	1	100.00
		uart_csr_aliasing	1.530s	39.102us	1	1	100.00
		uart_same_csr_outstanding	1.760s	24.943us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.590s	29.502us	1	1	100.00
		uart_csr_rw	1.660s	12.987us	1	1	100.00
		uart_csr_aliasing	1.530s	39.102us	1	1	100.00
		uart_same_csr_outstanding	1.760s	24.943us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.730s	489.452us	1	1	100.00
		uart_tl_intg_err	2.270s	608.109us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.270s	608.109us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.074m	5.714ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00