CHIP Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: `5c5f5a8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.602m	3.736ms	1	1	100.00
		chip_sw_example_rom	1.349m	2.532ms	1	1	100.00
		chip_sw_example_manufacturer	2.061m	3.080ms	1	1	100.00
		chip_sw_example_concurrency	2.092m	3.249ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.241m	7.344ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.296m	5.802ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	52.091m	43.583ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.154h	35.869ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.755m	6.759ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.154h	35.869ms	1	1	100.00
		chip_csr_rw	5.296m	5.802ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	8.810s	158.520us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.684m	3.543ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.684m	3.543ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.684m	3.543ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.285m	4.669ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.285m	4.669ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.717m	4.568ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.621m	4.194ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.620m	5.128ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.527m	3.960ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.499m	8.522ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.909m	4.190ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.066m	4.813ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.066m	4.813ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.428m	2.815ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.427m	6.710ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.651m	4.212ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.748m	14.200ms	1	1	100.00
		chip_tap_straps_testunlock0	5.725m	6.392ms	1	1	100.00
		chip_tap_straps_rma	4.559m	4.812ms	1	1	100.00
		chip_tap_straps_prod	1.451m	2.390ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.124m	3.433ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.215m	9.556ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.550m	4.440ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.550m	4.440ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.316m	7.752ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	23.703m	17.214ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.635m	3.854ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.653m	5.993ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.991m	18.336ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.532m	3.213ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.740m	6.021ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.525m	3.261ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.832m	7.994ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.189m	2.474ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.735m	4.058ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.071m	2.113ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.580m	3.540ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.575m	5.566ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.935m	4.659ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.524m	2.934ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.935m	4.659ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.650m	3.189ms	1	1	100.00
		chip_sw_aes_smoketest	2.164m	2.934ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.979m	3.074ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.816m	2.809ms	1	1	100.00
		chip_sw_csrng_smoketest	2.915m	3.145ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.960m	3.188ms	1	1	100.00
		chip_sw_gpio_smoketest	2.248m	2.720ms	1	1	100.00
		chip_sw_hmac_smoketest	3.184m	3.598ms	1	1	100.00
		chip_sw_kmac_smoketest	2.731m	2.587ms	1	1	100.00
		chip_sw_otbn_smoketest	16.612m	9.772ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.569m	6.347ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.145m	5.515ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.109m	2.246ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.563m	3.758ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.591m	2.251ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.602m	2.045ms	1	1	100.00
		chip_sw_uart_smoketest	2.869m	2.878ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.274m	2.360ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.147m	3.667ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.990h	61.675ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.593m	15.421ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.647m	6.123ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.191m	3.417ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.865m	3.108ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.780h	54.831ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.904h	55.718ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	51.390s	2.101ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	51.390s	2.101ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.154h	35.869ms	1	1	100.00
		chip_same_csr_outstanding	20.883m	14.951ms	1	1	100.00
		chip_csr_hw_reset	3.241m	7.344ms	1	1	100.00
		chip_csr_rw	5.296m	5.802ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.154h	35.869ms	1	1	100.00
		chip_same_csr_outstanding	20.883m	14.951ms	1	1	100.00
		chip_csr_hw_reset	3.241m	7.344ms	1	1	100.00
		chip_csr_rw	5.296m	5.802ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	27.410s	1.077ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.430s	51.129us	1	1	100.00
		xbar_smoke_large_delays	1.070m	11.097ms	1	1	100.00
		xbar_smoke_slow_rsp	55.990s	6.836ms	1	1	100.00
		xbar_random_zero_delays	19.110s	292.513us	1	1	100.00
		xbar_random_large_delays	2.576m	26.634ms	1	1	100.00
		xbar_random_slow_rsp	2.111m	15.744ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.800s	333.056us	1	1	100.00
		xbar_error_and_unmapped_addr	11.430s	143.204us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	36.850s	1.929ms	1	1	100.00
		xbar_error_and_unmapped_addr	11.430s	143.204us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	46.780s	773.060us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.112m	53.801ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	53.770s	2.585ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.045m	3.158ms	1	1	100.00
		xbar_stress_all_with_error	1.365m	4.694ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.708m	3.245ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.227m	1.723ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.593m	15.421ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.132m	24.738ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.186m	14.320ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.462m	12.168ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.628m	15.717ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.392m	15.610ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.709m	15.252ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.505m	15.087ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.460s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	30.630s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.850s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	32.120s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.210s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.490s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	29.680s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.780s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.120s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.620s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.310s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.610s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.630s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.520s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.890s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.860s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.910s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.420s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.780s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.480s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.760s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.230s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.580s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.040s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.730s	10.100us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.556m	11.213ms	1	1	100.00
		rom_e2e_asm_init_dev	35.782m	15.332ms	1	1	100.00
		rom_e2e_asm_init_prod	37.384m	15.525ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.060m	14.923ms	1	1	100.00
		rom_e2e_asm_init_rma	36.600m	14.723ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.255m	15.501ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.506m	14.898ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.117m	15.326ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.152m	15.580ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.966m	34.406ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.966m	34.406ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.102m	3.073ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.532m	3.213ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.318m	2.536ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.485m	3.281ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.731m	8.442ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.191m	2.310ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.710m	5.680ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.042m	5.669ms	1	1	100.00
		chip_plic_all_irqs_10	4.558m	3.207ms	1	1	100.00
		chip_plic_all_irqs_20	5.680m	4.006ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.757m	3.428ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.774m	10.414ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.063m	2.908ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.837m	2.237ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.815m	12.133ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.903m	5.833ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.966m	6.985ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.338m	7.418ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.933h	254.761ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.694m	3.751ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.569m	6.347ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.694m	3.751ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.148m	9.847ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.148m	9.847ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.326m	7.893ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.150m	6.080ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.489m	5.671ms	1	1	100.00
		chip_sw_aes_idle	2.485m	3.281ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.140m	2.663ms	1	1	100.00
		chip_sw_kmac_idle	2.892m	2.972ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.474m	4.657ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.002m	4.187ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.873m	4.506ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.962m	5.250ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.588m	8.222ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.851m	3.680ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.758m	4.763ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.673m	4.573ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.488m	3.777ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.417m	4.500ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.365m	4.634ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.316m	7.752ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.207m	11.817ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.673m	4.573ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.488m	3.777ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.635m	3.854ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.653m	5.993ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.991m	18.336ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.532m	3.213ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.740m	6.021ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.525m	3.261ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.832m	7.994ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.189m	2.474ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.735m	4.058ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.071m	2.113ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.060m	2.490ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.412m	4.306ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.277m	7.340ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.070m	24.063ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.399m	3.700ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.154m	2.606ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	15.656m	9.783ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.877m	2.787ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.751m	5.943ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.952m	17.587ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	54.774m	35.976ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.316m	7.752ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.529m	4.635ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.885m	3.739ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	10.903m	5.833ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.021m	6.947ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.930m	2.980ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.316m	5.279ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.314m	2.745ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	31.961m	13.025ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.080m	2.178ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.319m	7.097ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.080m	2.178ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.021m	6.947ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.167m	2.928ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.656m	16.436ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.249m	5.358ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.653m	5.993ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.703m	3.748ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.635m	3.854ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.618m	42.549ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.656m	16.436ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.630m	3.431ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.676m	9.937ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.713m	5.557ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.618m	42.549ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.713m	5.557ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.713m	5.557ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.713m	5.557ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.713m	5.557ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.463m	9.719ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.044m	4.961ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.548m	4.440ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.548m	4.440ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.065m	3.027ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.525m	3.261ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.140m	2.663ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.462m	2.429ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.922m	3.942ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.194m	5.276ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.055m	4.732ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.494m	5.241ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.668m	4.345ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.676m	9.937ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.832m	7.994ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	18.758m	10.216ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.731m	8.442ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	41.523m	15.087ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.108m	2.296ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.767m	3.574ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.189m	2.474ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.676m	9.937ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.706m	2.960ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	22.112m	9.673ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.892m	2.972ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.710m	5.680ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.748m	14.200ms	1	1	100.00
		chip_tap_straps_rma	4.559m	4.812ms	1	1	100.00
		chip_tap_straps_prod	1.451m	2.390ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.287m	2.633ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	19.253m	9.644ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.713m	5.557ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.618m	42.549ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.758m	3.640ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.742m	7.483ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.038m	5.224ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.987m	7.028ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.676m	9.937ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.544m	8.562ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.510m	9.126ms	1	1	100.00
		chip_prim_tl_access	3.463m	9.719ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.207m	11.817ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.851m	3.680ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.758m	4.763ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.673m	4.573ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.488m	3.777ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.417m	4.500ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.365m	4.634ms	1	1	100.00
		chip_tap_straps_dev	14.748m	14.200ms	1	1	100.00
		chip_tap_straps_rma	4.559m	4.812ms	1	1	100.00
		chip_tap_straps_prod	1.451m	2.390ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.554m	13.997ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.068m	3.574ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.696m	3.611ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.581m	2.283ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.422m	3.883ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.933m	21.294ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.554m	13.997ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.069h	50.160ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	59.323m	46.001ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.882m	10.173ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.003h	45.747ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.933m	21.294ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.409m	3.040ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.208m	2.857ms	1	1	100.00
		rom_volatile_raw_unlock	1.178m	2.692ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.305m	16.858ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.991m	18.336ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.489m	5.671ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.489m	5.671ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.489m	5.671ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.138m	3.391ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.656m	16.436ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.138m	3.391ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.676m	9.937ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.697m	4.285ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.321m	3.059ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.656m	16.436ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.138m	3.391ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.676m	9.937ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.697m	4.285ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.321m	3.059ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.450m	4.168ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.287m	2.633ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.758m	3.640ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.742m	7.483ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.038m	5.224ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.987m	7.028ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.017m	5.511ms	1	1	100.00
		chip_prim_tl_access	3.463m	9.719ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.463m	9.719ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.219m	8.749ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.169m	7.364ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	19.328m	25.206ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.745m	6.777ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.119m	9.134ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.206m	6.224ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.647m	24.855ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.274m	16.006ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.148m	9.847ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.208m	11.567ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.369m	4.329ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.169m	7.364ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.100m	4.599ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.833m	35.706ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.589m	5.774ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.724m	5.555ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.632m	20.444ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.863m	7.101ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.398m	10.719ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	26.908m	31.116ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.619m	3.473ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.544m	8.562ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.544m	8.562ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.398m	10.719ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.632m	20.444ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.369m	4.329ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.569m	6.347ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.063m	3.895ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.441m	4.001ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.273m	4.829ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.774m	10.414ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.024m	2.806ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.966m	6.985ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.069m	4.651ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.473m	4.556ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.696m	2.897ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.321m	3.059ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.441m	4.001ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.441m	4.001ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	20.698m	18.603ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.706m	13.496ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.063m	3.895ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.885m	4.798ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.647m	6.710ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.559m	4.812ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.554m	13.997ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.042m	5.669ms	1	1	100.00
		chip_plic_all_irqs_10	4.558m	3.207ms	1	1	100.00
		chip_plic_all_irqs_20	5.680m	4.006ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.921m	3.179ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.559m	2.547ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.593m	15.421ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.083m	7.140ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.007m	2.374ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.386m	2.978ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.685m	2.381ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.697m	4.285ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.735m	4.058ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.106m	8.913ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.260m	8.092ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.510m	9.126ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.550m	4.440ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.863m	7.101ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.597m	24.768ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.447m	2.819ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.993m	3.489ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.576m	4.183ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.597m	24.768ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.597m	24.768ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.660m	20.633ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.660m	20.633ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	6.085m	6.971ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.966m	34.406ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.156m	2.716ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.233m	2.643ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.386m	3.470ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.791m	3.494ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.953m	8.178ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.314h	31.138ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.033m	12.120ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.526m	2.922ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.450m	3.473ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.679m	2.460ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.355h	71.417ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.102m	3.677ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.132m	11.150ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.345m	11.446ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.009m	10.745ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.582m	3.237ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.154m	4.227ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.275m	4.352ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.671s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.440m	5.022ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.895m	3.203ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.729m	6.361ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.276m	7.877ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.544m	2.167ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.111m	4.789ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.997m	3.150ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.589m	5.907ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.766m	6.678ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.179m	3.742ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.398m	10.719ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.132m	11.150ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.345m	11.446ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.009m	10.745ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	20.493s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.947m	6.027ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.410h	38.377ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.410h	38.377ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.100m	3.384ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.285m	4.669ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.071m	18.773ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.741m	3.043ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.366m	5.350ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.183m	3.356ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.893m	2.471ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.172m	3.859ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.666s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.805m	2.845ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.89247865954707389395791715576524384879396535591964739275076080469709696085074
    Line 679, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.106079617979939618592227687028212786068924855898307047407086488557891180283482
    Line 607, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.45688942553862296900128521016464992139890657226358474711841908957050965462879
    Line 650, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.32539989536782564315561318907999619951025848250598888720215282524945297777863
    Line 698, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.16963526377247285804723144719863068062500151253279827262988497271096465196941
    Line 612, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.87416318040295778426981800278097958000042809162701047069700110657563134399320
    Line 599, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.101797551123463094378786918221977925300761252092022083838573836336312208849289
    Line 617, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.77421782818124580970856351856830943736138280106538775228674960979027860647758
    Line 616, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.111052558892859799763051601721893605155637799042410734157055028033437268143970
    Line 628, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.20257520132867602983884072535652538995508793731121907321986448287293945083923
    Line 620, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 3 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.54385841418159783674620355607898115225484735311185136606312260675831744645680
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.151s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rv_dm_access_after_escalation_reset has 1 failures.

0.chip_sw_rv_dm_access_after_escalation_reset.25341449628480779048340069513239594837647234247636890651697350982576613374036
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log

    bazel-bin/sw/device/tests/alert_handler_escalation_test_sim_dv.bash
  INFO: Elapsed time: 3.390s, Critical Path: 2.73s
  INFO: 3 processes: 1984 action cache hit, 1 internal, 2 processwrapper-sandbox.
  INFO: Build completed successfully, 3 total actions
  WARNING: Build options --//util/design/data:img_seed and --define have changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:458:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  WARNING: Build options --//util/design/data:img_seed and --define have changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:458:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  cp: cannot stat 'bazel-out/k8-fastbuild-ST-1df456420242/bin/hw/top_earlgrey/data/otp/img_rma.24.vmem': No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.52873559894628195194354568879267247857397554975316646484634172692183554794792
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 1.455s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1172618347762192213285078239506033222345470466866578844573470267443286956080
    Line 712, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.45544897507612340078897925153973117025785052472032248192429043767944828366352
    Line 657, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2137417275937894527988206447100394404471347251715247064970916516537814567280
    Line 704, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.97573747469616410532459909821087680950934152181303671060905143028535172248031
    Line 819, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.85784132262016187204656378155750352808299493562705933582497733464137705422782
    Line 753, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.37689800103986076554882211834811419759512260426317224736946258763925785161673
    Line 874, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.69322725689145835389669944650754852706108625208920313713910341704985176452541
    Line 588, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.1231011116395853164904982981643029910253928539227554141843414106885721280060
    Line 678, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2814.854500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2814.854500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.14533082938758373820844787647988926795421889377336525209639899478026155892400
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2373.912560 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2373.912560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86245) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.94202129597741868557796040152830691926445283650425257015225460671112577142985
Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4001.208260 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86245) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4001.208260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.55555154900142847357073482971455611393774231216277731154745425911063515919800
    Line 437, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34405.585553 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34405.585553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.55943704837536172204874082451110228061132176030054288596346209572895857531632
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2309.716740 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2309.716740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.76621874814357126658837975363147160080816447732296511902035817919714855891914
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2237.108300 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2237.108300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.85661121381208518493767444236911561196551287043267481644797219430092977775686
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2980.266580 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2980.266580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40601) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.63560437171780442393976794631474231635174399892059577401798082825045482706070
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2101.114608 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40601) { a_addr: 'h10454  a_data: 'hb9d7683  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h19564  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2101.114608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.88073088104713269406231890128753075514644151624184756507607943187493056443261
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3416.642500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3416.642500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.85048978492496551972668230242200812334359681912863781681774954202638463551893
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3108.500000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3108.500000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.43474951666386248150436628494149079214033166877392688251941870722675698602599
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17214.439939 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17214.439939 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.21234178222349599450896156699058846763693039464376045997391752056502333228454
    Line 479, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3677.116598 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3677.116598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.30298771648944156488738094036436233181442507305004804495089391274742606861861
    Line 689, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.8901924678087864773640201907556696850420556606387525721801152515453551815646
    Line 700, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```