ADC_CTRL Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	14.380s	5.847ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.900s	837.629us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	576.430us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	41.800s	26.952ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.930s	1.172ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.970s	463.379us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	576.430us	1	1	100.00
		adc_ctrl_csr_aliasing	5.930s	1.172ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.936m	167.278ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.534m	330.435ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	14.535m	487.649ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.236m	162.919ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.356m	525.956ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	16.583m	605.840ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.366m	328.218ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	8.384m	351.273ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	5.990s	3.778ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	42.090s	25.612ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	34.640s	78.994ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.350s	6.583ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.890s	331.675us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.950s	493.954us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.680s	580.084us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.680s	580.084us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.900s	837.629us	1	1	100.00
		adc_ctrl_csr_rw	1.920s	576.430us	1	1	100.00
		adc_ctrl_csr_aliasing	5.930s	1.172ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.240s	3.108ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.900s	837.629us	1	1	100.00
		adc_ctrl_csr_rw	1.920s	576.430us	1	1	100.00
		adc_ctrl_csr_aliasing	5.930s	1.172ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.240s	3.108ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.220s	4.372ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.410s	8.510ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.410s	8.510ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	21.550s	35.755ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00