EDN Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.990s	15.725us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.710s	17.274us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.770s	23.624us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.380s	65.651us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.060s	22.017us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.030s	42.942us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.770s	23.624us	1	1	100.00
		edn_csr_aliasing	2.060s	22.017us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.820s	60.254us	1	1	100.00
V2	csrng_commands	edn_genbits	1.820s	60.254us	1	1	100.00
V2	genbits	edn_genbits	1.820s	60.254us	1	1	100.00
V2	interrupts	edn_intr	1.850s	36.522us	1	1	100.00
V2	alerts	edn_alert	2.030s	67.738us	1	1	100.00
V2	errs	edn_err	2.080s	26.158us	1	1	100.00
V2	disable	edn_disable	1.710s	65.114us	1	1	100.00
		edn_disable_auto_req_mode	2.070s	88.236us	1	1	100.00
V2	stress_all	edn_stress_all	2.560s	188.452us	1	1	100.00
V2	intr_test	edn_intr_test	1.810s	28.652us	1	1	100.00
V2	alert_test	edn_alert_test	1.900s	17.909us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.100s	220.266us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.100s	220.266us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.710s	17.274us	1	1	100.00
		edn_csr_rw	1.770s	23.624us	1	1	100.00
		edn_csr_aliasing	2.060s	22.017us	1	1	100.00
		edn_same_csr_outstanding	1.820s	20.540us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.710s	17.274us	1	1	100.00
		edn_csr_rw	1.770s	23.624us	1	1	100.00
		edn_csr_aliasing	2.060s	22.017us	1	1	100.00
		edn_same_csr_outstanding	1.820s	20.540us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.770s	1.002ms	1	1	100.00
		edn_tl_intg_err	2.260s	161.438us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.970s	176.501us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.030s	67.738us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.770s	1.002ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.770s	1.002ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.770s	1.002ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.770s	1.002ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.030s	67.738us	1	1	100.00
		edn_sec_cm	6.770s	1.002ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.030s	67.738us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.260s	161.438us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	23.770s	5.131ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00