HMAC Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.590s 274.906us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.930s 28.651us 1 1 100.00
V1 csr_rw hmac_csr_rw 2.030s 104.072us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.150s 325.357us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.280s 442.400us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 5.487m 88.871ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 2.030s 104.072us 1 1 100.00
hmac_csr_aliasing 7.280s 442.400us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 46.210s 1.151ms 1 1 100.00
V2 back_pressure hmac_back_pressure 50.810s 2.606ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.252m 24.282ms 1 1 100.00
hmac_test_sha384_vectors 21.120s 1.509ms 1 1 100.00
hmac_test_sha512_vectors 5.630m 10.080ms 1 1 100.00
hmac_test_hmac256_vectors 13.760s 1.762ms 1 1 100.00
hmac_test_hmac384_vectors 10.380s 336.963us 1 1 100.00
hmac_test_hmac512_vectors 9.110s 937.626us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.040s 1.724ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 12.943m 19.950ms 1 1 100.00
V2 error hmac_error 41.010s 2.081ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 18.380s 2.485ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.590s 274.906us 1 1 100.00
hmac_long_msg 46.210s 1.151ms 1 1 100.00
hmac_back_pressure 50.810s 2.606ms 1 1 100.00
hmac_datapath_stress 12.943m 19.950ms 1 1 100.00
hmac_burst_wr 10.040s 1.724ms 1 1 100.00
hmac_stress_all 19.137m 38.909ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.590s 274.906us 1 1 100.00
hmac_long_msg 46.210s 1.151ms 1 1 100.00
hmac_back_pressure 50.810s 2.606ms 1 1 100.00
hmac_datapath_stress 12.943m 19.950ms 1 1 100.00
hmac_wipe_secret 18.380s 2.485ms 1 1 100.00
hmac_test_sha256_vectors 3.252m 24.282ms 1 1 100.00
hmac_test_sha384_vectors 21.120s 1.509ms 1 1 100.00
hmac_test_sha512_vectors 5.630m 10.080ms 1 1 100.00
hmac_test_hmac256_vectors 13.760s 1.762ms 1 1 100.00
hmac_test_hmac384_vectors 10.380s 336.963us 1 1 100.00
hmac_test_hmac512_vectors 9.110s 937.626us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.590s 274.906us 1 1 100.00
hmac_long_msg 46.210s 1.151ms 1 1 100.00
hmac_back_pressure 50.810s 2.606ms 1 1 100.00
hmac_datapath_stress 12.943m 19.950ms 1 1 100.00
hmac_burst_wr 10.040s 1.724ms 1 1 100.00
hmac_error 41.010s 2.081ms 1 1 100.00
hmac_wipe_secret 18.380s 2.485ms 1 1 100.00
hmac_test_sha256_vectors 3.252m 24.282ms 1 1 100.00
hmac_test_sha384_vectors 21.120s 1.509ms 1 1 100.00
hmac_test_sha512_vectors 5.630m 10.080ms 1 1 100.00
hmac_test_hmac256_vectors 13.760s 1.762ms 1 1 100.00
hmac_test_hmac384_vectors 10.380s 336.963us 1 1 100.00
hmac_test_hmac512_vectors 9.110s 937.626us 1 1 100.00
hmac_stress_all 19.137m 38.909ms 1 1 100.00
V2 stress_all hmac_stress_all 19.137m 38.909ms 1 1 100.00
V2 alert_test hmac_alert_test 1.650s 13.332us 1 1 100.00
V2 intr_test hmac_intr_test 1.540s 13.481us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.360s 166.511us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.360s 166.511us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.930s 28.651us 1 1 100.00
hmac_csr_rw 2.030s 104.072us 1 1 100.00
hmac_csr_aliasing 7.280s 442.400us 1 1 100.00
hmac_same_csr_outstanding 3.700s 152.301us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.930s 28.651us 1 1 100.00
hmac_csr_rw 2.030s 104.072us 1 1 100.00
hmac_csr_aliasing 7.280s 442.400us 1 1 100.00
hmac_same_csr_outstanding 3.700s 152.301us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.810s 107.648us 1 1 100.00
hmac_tl_intg_err 3.410s 97.556us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.410s 97.556us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.590s 274.906us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.960s 40.301us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.779m 105.053ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.920s 115.934us 1 1 100.00
TOTAL 28 28 100.00