I2C Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: `12e45f3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.250s	6.089ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.660s	7.031ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.530s	21.408us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	18.508us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.860s	734.948us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.390s	433.096us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.740s	31.557us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	18.508us	1	1	100.00
		i2c_csr_aliasing	2.390s	433.096us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	11.020s	528.178us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	17.618m	24.892ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.868m	50.880ms	1	1	100.00
V2	host_override	i2c_host_override	1.520s	40.686us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.543m	22.898ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	51.790s	11.116ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.770s	345.572us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.980s	2.629ms	1	1	100.00
		i2c_host_fifo_reset_rx	8.500s	230.362us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.124m	12.647ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.340s	1.016ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.330s	103.310us	1	1	100.00
V2	target_glitch	i2c_target_glitch	10.730s	2.242ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	32.110s	27.184ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.650s	5.437ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	50.570s	3.342ms	1	1	100.00
		i2c_target_intr_smoke	6.090s	4.891ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.300s	650.857us	1	1	100.00
		i2c_target_fifo_reset_tx	2.280s	809.904us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.452m	39.274ms	1	1	100.00
		i2c_target_stress_rd	50.570s	3.342ms	1	1	100.00
		i2c_target_intr_stress_wr	4.311m	23.541ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.110s	1.328ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	29.930s	4.082ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.510s	1.818ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.440s	285.843us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.480s	1.732ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.930s	524.957us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.868m	50.880ms	1	1	100.00
		i2c_host_perf_precise	1.860s	57.403us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.340s	1.016ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.460s	87.431us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.860s	976.746us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.870s	2.263ms	1	1	100.00
		i2c_target_nack_txstretch	1.950s	158.962us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	14.220s	513.791us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.680s	2.041ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	34.506us	1	1	100.00
V2	intr_test	i2c_intr_test	1.660s	44.703us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.330s	181.376us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.330s	181.376us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.530s	21.408us	1	1	100.00
		i2c_csr_rw	1.660s	18.508us	1	1	100.00
		i2c_csr_aliasing	2.390s	433.096us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	115.102us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.530s	21.408us	1	1	100.00
		i2c_csr_rw	1.660s	18.508us	1	1	100.00
		i2c_csr_aliasing	2.390s	433.096us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	115.102us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.080s	361.365us	1	1	100.00
		i2c_sec_cm	1.910s	221.550us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.080s	361.365us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.720s	3.002ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.390s	263.125us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	24.080s	3.359ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.8604312633607622971267624615966453635589326475807571384182967568659200335456
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3002327645 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3002327645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.90615697464960568177706259613734761081846585109625087118032771394926720889748
    Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3358519324 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3358519324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.17344600364746357432758984311595662831071064381022159125390659009708408096634
Line 245, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 24892401744 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @30856830

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.29095583346909088682231918857900261060167003867536970248361638468644752583314
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 263125229 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 263125229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```