KEYMGR Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	5.180s	161.054us	1	1	100.00
V1	random	keymgr_random	4.780s	469.190us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.990s	40.995us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.670s	60.981us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.610s	593.694us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.360s	196.640us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.110s	31.133us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.670s	60.981us	1	1	100.00
		keymgr_csr_aliasing	4.360s	196.640us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.420s	194.343us	1	1	100.00
V2	sideload	keymgr_sideload	4.940s	114.740us	1	1	100.00
		keymgr_sideload_kmac	3.570s	124.146us	1	1	100.00
		keymgr_sideload_aes	4.380s	400.852us	1	1	100.00
		keymgr_sideload_otbn	5.290s	236.858us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.530s	103.726us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.960s	128.153us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.880s	223.463us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.860s	198.847us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.000s	43.965us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.470s	126.588us	1	1	100.00
V2	stress_all	keymgr_stress_all	11.340s	834.292us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.800s	13.406us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.840s	50.522us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.730s	271.758us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.730s	271.758us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.990s	40.995us	1	1	100.00
		keymgr_csr_rw	1.670s	60.981us	1	1	100.00
		keymgr_csr_aliasing	4.360s	196.640us	1	1	100.00
		keymgr_same_csr_outstanding	2.410s	95.722us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.990s	40.995us	1	1	100.00
		keymgr_csr_rw	1.670s	60.981us	1	1	100.00
		keymgr_csr_aliasing	4.360s	196.640us	1	1	100.00
		keymgr_same_csr_outstanding	2.410s	95.722us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
		keymgr_tl_intg_err	5.720s	219.373us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.710s	133.731us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.710s	133.731us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.710s	133.731us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.710s	133.731us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.160s	471.518us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.720s	219.373us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.710s	133.731us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.420s	194.343us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.780s	469.190us	1	1	100.00
		keymgr_csr_rw	1.670s	60.981us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.780s	469.190us	1	1	100.00
		keymgr_csr_rw	1.670s	60.981us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.780s	469.190us	1	1	100.00
		keymgr_csr_rw	1.670s	60.981us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.960s	128.153us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.000s	43.965us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.000s	43.965us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.780s	469.190us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.170s	42.088us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.360s	46.502us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.960s	128.153us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.360s	46.502us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.360s	46.502us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.360s	46.502us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.140s	513.621us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.360s	46.502us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.680s	522.063us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.106293033399714809694101509973031267546864354062562319638649923773163383995447
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
        UVM_ERROR @  95722285 ps: (keymgr_csr_assert_fpv.sv:439) [ASSERT FAILED] attest_sw_binding_1_rd_A
        UVM_INFO @  95722285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---