KMAC/MASKED Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	9.110s	1.911ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	61.332us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.930s	41.411us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.100s	1.459ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.150s	528.462us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.850s	337.927us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.930s	41.411us	1	1	100.00
		kmac_csr_aliasing	7.150s	528.462us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.900s	26.727us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.420s	166.546us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	10.665m	16.657ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.131m	6.857ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.104m	92.443ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.988m	443.783ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.850s	2.125ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.270s	538.206us	1	1	100.00
		kmac_test_vectors_shake_128	28.501m	22.256ms	1	1	100.00
		kmac_test_vectors_shake_256	31.061m	357.722ms	1	1	100.00
		kmac_test_vectors_kmac	3.020s	371.285us	1	1	100.00
		kmac_test_vectors_kmac_xof	4.350s	522.873us	1	1	100.00
V2	sideload	kmac_sideload	4.454m	9.274ms	1	1	100.00
V2	app	kmac_app	1.159m	14.322ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.453m	14.977ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.743m	55.715ms	1	1	100.00
V2	error	kmac_error	1.291m	5.117ms	1	1	100.00
V2	key_error	kmac_key_error	9.730s	3.398ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.220s	66.935us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.700s	9.245ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.350s	2.032ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	5.040s	266.845us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.980s	90.563us	1	1	100.00
V2	stress_all	kmac_stress_all	20.041m	64.513ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.740s	41.074us	1	1	100.00
V2	alert_test	kmac_alert_test	1.720s	17.024us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.040s	76.992us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.040s	76.992us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	61.332us	1	1	100.00
		kmac_csr_rw	1.930s	41.411us	1	1	100.00
		kmac_csr_aliasing	7.150s	528.462us	1	1	100.00
		kmac_same_csr_outstanding	2.760s	88.303us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	61.332us	1	1	100.00
		kmac_csr_rw	1.930s	41.411us	1	1	100.00
		kmac_csr_aliasing	7.150s	528.462us	1	1	100.00
		kmac_same_csr_outstanding	2.760s	88.303us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.170s	209.805us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.170s	209.805us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.170s	209.805us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.170s	209.805us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.770s	894.921us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	42.240s	4.885ms	1	1	100.00
		kmac_tl_intg_err	4.310s	158.886us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.310s	158.886us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.980s	90.563us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	9.110s	1.911ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.454m	9.274ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.170s	209.805us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.240s	4.885ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.240s	4.885ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.240s	4.885ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	9.110s	1.911ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.980s	90.563us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.240s	4.885ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	41.310s	4.131ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	9.110s	1.911ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	9.440s	2.212ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.5639138552184066325251426262324454089177319716019814258455096464600180797282
      Line 101, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2211733325 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2211733325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---