KMAC/UNMASKED Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.520s	425.150us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	56.347us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.860s	62.950us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.340s	302.386us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.370s	714.488us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.260s	38.135us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.860s	62.950us	1	1	100.00
		kmac_csr_aliasing	4.370s	714.488us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	88.242us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.120s	29.337us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.322m	307.382ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.177m	89.319ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.130s	7.381ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.460s	1.664ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.880s	4.529ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.280s	2.377ms	1	1	100.00
		kmac_test_vectors_shake_128	2.177m	13.628ms	1	1	100.00
		kmac_test_vectors_shake_256	22.556m	117.398ms	1	1	100.00
		kmac_test_vectors_kmac	2.550s	36.711us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.310s	76.632us	1	1	100.00
V2	sideload	kmac_sideload	46.180s	9.574ms	1	1	100.00
V2	app	kmac_app	1.281m	7.852ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.249m	1.964ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.775m	8.015ms	1	1	100.00
V2	error	kmac_error	4.974m	50.985ms	1	1	100.00
V2	key_error	kmac_key_error	7.060s	3.282ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.250s	198.552us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	6.580s	488.275us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.030s	452.615us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	37.220s	24.162ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.970s	57.149us	1	1	100.00
V2	stress_all	kmac_stress_all	4.991m	65.003ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.510s	42.131us	1	1	100.00
V2	alert_test	kmac_alert_test	1.610s	55.038us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.180s	451.735us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.180s	451.735us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	56.347us	1	1	100.00
		kmac_csr_rw	1.860s	62.950us	1	1	100.00
		kmac_csr_aliasing	4.370s	714.488us	1	1	100.00
		kmac_same_csr_outstanding	2.890s	784.077us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	56.347us	1	1	100.00
		kmac_csr_rw	1.860s	62.950us	1	1	100.00
		kmac_csr_aliasing	4.370s	714.488us	1	1	100.00
		kmac_same_csr_outstanding	2.890s	784.077us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.380s	338.863us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.380s	338.863us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.380s	338.863us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.380s	338.863us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	406.299us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	48.610s	5.741ms	1	1	100.00
		kmac_tl_intg_err	3.870s	426.241us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.870s	426.241us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.970s	57.149us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.520s	425.150us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	46.180s	9.574ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.380s	338.863us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.610s	5.741ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.610s	5.741ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.610s	5.741ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.520s	425.150us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.970s	57.149us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.610s	5.741ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.337m	24.541ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.520s	425.150us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.460s	201.001us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.94927968592244033224809889513707855029658924155683343437610859675220576612431
      Line 101, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 201001421 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 201001421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---