ROM_CTRL/32KB Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.970s 417.443us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.060s 375.913us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.800s 556.701us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.290s 131.030us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.380s 1.073ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.070s 583.887us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.800s 556.701us 1 1 100.00
rom_ctrl_csr_aliasing 4.380s 1.073ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.930s 358.618us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.000s 696.559us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.660s 545.754us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 17.760s 2.289ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.380s 742.804us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.790s 136.973us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.380s 165.149us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.380s 165.149us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.060s 375.913us 1 1 100.00
rom_ctrl_csr_rw 4.800s 556.701us 1 1 100.00
rom_ctrl_csr_aliasing 4.380s 1.073ms 1 1 100.00
rom_ctrl_same_csr_outstanding 4.690s 270.139us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.060s 375.913us 1 1 100.00
rom_ctrl_csr_rw 4.800s 556.701us 1 1 100.00
rom_ctrl_csr_aliasing 4.380s 1.073ms 1 1 100.00
rom_ctrl_same_csr_outstanding 4.690s 270.139us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.180s 1.149ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.645m 550.947us 1 1 100.00
rom_ctrl_tl_intg_err 22.950s 434.074us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.645m 550.947us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.645m 550.947us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.645m 550.947us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.645m 550.947us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.970s 417.443us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.970s 417.443us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.970s 417.443us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 22.950s 434.074us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.380s 742.804us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.025m 2.005ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.180s 1.149ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.645m 550.947us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.048m 1.865ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00