ROM_CTRL/64KB Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.490s 350.088us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.400s 210.413us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 8.080s 319.507us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.070s 377.250us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.610s 1.575ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.980s 288.846us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.080s 319.507us 1 1 100.00
rom_ctrl_csr_aliasing 6.610s 1.575ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 9.440s 1.031ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.580s 297.746us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.780s 435.602us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.930s 818.647us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.260s 392.698us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.820s 1.024ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.550s 295.307us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.550s 295.307us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.400s 210.413us 1 1 100.00
rom_ctrl_csr_rw 8.080s 319.507us 1 1 100.00
rom_ctrl_csr_aliasing 6.610s 1.575ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.730s 302.511us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.400s 210.413us 1 1 100.00
rom_ctrl_csr_rw 8.080s 319.507us 1 1 100.00
rom_ctrl_csr_aliasing 6.610s 1.575ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.730s 302.511us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 33.050s 1.120ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.583m 918.464us 1 1 100.00
rom_ctrl_tl_intg_err 36.680s 290.004us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.583m 918.464us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.583m 918.464us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.583m 918.464us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.583m 918.464us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.490s 350.088us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.490s 350.088us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.490s 350.088us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.680s 290.004us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.260s 392.698us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.861m 6.812ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 33.050s 1.120ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.583m 918.464us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.156m 12.421ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00