RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.060s 494.625us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.700s 283.618us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.710s 133.593us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 11.240s 4.515ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 6.420s 2.298ms 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 19.040s 9.840ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.350s 3.225ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 50.130s 44.316ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.831m 165.878ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.730s 321.292us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.960s 146.514us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.270s 133.340us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.740s 129.369us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.630s 124.824us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.110s 825.046us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.650s 115.543us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.550s 734.058us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.730s 321.292us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.860s 99.913us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.030s 1.195ms 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.270s 133.340us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.880s 210.307us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.830s 240.273us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 3.570s 247.988us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 20.810s 2.956ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 42.990s 2.209ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.500s 602.160us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 42.990s 2.209ms 1 1 100.00
rv_dm_csr_rw 3.570s 247.988us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.750s 69.736us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.680s 31.774us 1 1 100.00
V1 TOTAL 27 27 100.00
V2 idcode rv_dm_smoke 2.060s 494.625us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.010s 357.550us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.040s 502.333us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.720s 134.404us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.460s 869.768us 1 1 100.00
V2 sba rv_dm_sba_tl_access 8.620s 3.703ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.530s 52.892us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 7.810s 3.436ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.050s 278.959us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.740s 131.008us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 9.810s 4.508ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.130s 776.986us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.620s 91.437us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 4.970s 2.932ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.970s 94.217us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.700s 166.635us 1 1 100.00
V2 stress_all rv_dm_stress_all 5.440s 5.889ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.620s 47.922us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.780s 38.216us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.780s 38.216us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 42.990s 2.209ms 1 1 100.00
rv_dm_csr_hw_reset 2.830s 240.273us 1 1 100.00
rv_dm_csr_rw 3.570s 247.988us 1 1 100.00
rv_dm_same_csr_outstanding 6.340s 961.851us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 42.990s 2.209ms 1 1 100.00
rv_dm_csr_hw_reset 2.830s 240.273us 1 1 100.00
rv_dm_csr_rw 3.570s 247.988us 1 1 100.00
rv_dm_same_csr_outstanding 6.340s 961.851us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.590s 511.199us 1 1 100.00
rv_dm_tl_intg_err 13.410s 2.417ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 13.410s 2.417ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 9.810s 4.508ms 1 1 100.00
rv_dm_debug_disabled 1.650s 165.495us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 9.810s 4.508ms 1 1 100.00
rv_dm_debug_disabled 1.650s 165.495us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.060s 494.625us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.220s 245.382us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.690s 267.620us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.690s 267.620us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.220s 245.382us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.630s 53.336us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.940s 19.969us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets