RV_TIMER Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.600s	17.203us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.670s	15.189us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.560s	21.873us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.630s	65.190us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.570s	25.187us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.600s	123.883us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.560s	21.873us	1	1	100.00
		rv_timer_csr_aliasing	1.570s	25.187us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	7.380s	21.831ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.810s	836.595us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.269m	1.710s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.269m	1.710s	1	1	100.00
V2	stress	rv_timer_stress_all	3.990s	2.242ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.590s	19.574us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.610s	17.399us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.240s	116.924us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.240s	116.924us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.670s	15.189us	1	1	100.00
		rv_timer_csr_rw	1.560s	21.873us	1	1	100.00
		rv_timer_csr_aliasing	1.570s	25.187us	1	1	100.00
		rv_timer_same_csr_outstanding	1.630s	30.734us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.670s	15.189us	1	1	100.00
		rv_timer_csr_rw	1.560s	21.873us	1	1	100.00
		rv_timer_csr_aliasing	1.570s	25.187us	1	1	100.00
		rv_timer_same_csr_outstanding	1.630s	30.734us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.530s	220.848us	1	1	100.00
		rv_timer_tl_intg_err	1.720s	96.164us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.720s	96.164us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	26.240s	4.377ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.420s	41.858us	1	1	100.00
		rv_timer_max	1.560s	51.957us	1	1	100.00
		TOTAL			19	19	100.00