SPI_DEVICE/1R1W Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	16.620s	4.500ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.730s	23.439us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	219.792us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.660s	191.943us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.800s	3.038ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.660s	1.188ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	219.792us	1	1	100.00
		spi_device_csr_aliasing	14.800s	3.038ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.660s	75.134us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.000s	239.737us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.810s	37.121us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.530s	1.178us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.590s	6.067us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.490s	221.067us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.490s	221.067us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.770s	2.769ms	1	1	100.00
		spi_device_tpm_sts_read	1.640s	109.800us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.420s	3.484ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.400s	148.126us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.820s	116.812us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.820s	116.812us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.110s	230.036us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.110s	230.036us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.110s	230.036us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.110s	230.036us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.110s	230.036us	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	15.220s	10.309ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.870s	3.832ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.870s	3.832ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.870s	3.832ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.850s	156.626us	1	1	100.00
		spi_device_read_buffer_direct	4.100s	512.840us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.870s	3.832ms	1	1	100.00
		spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	quad_spi	spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	dual_spi	spi_device_flash_all	5.130s	868.967us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	7.260s	7.006ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	7.260s	7.006ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	16.620s	4.500ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	40.080s	6.331ms	1	1	100.00
V2	stress_all	spi_device_stress_all	30.570s	4.346ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.540s	141.086us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	51.772us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.170s	169.395us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.170s	169.395us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.730s	23.439us	1	1	100.00
		spi_device_csr_rw	2.860s	219.792us	1	1	100.00
		spi_device_csr_aliasing	14.800s	3.038ms	1	1	100.00
		spi_device_same_csr_outstanding	3.050s	43.125us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.730s	23.439us	1	1	100.00
		spi_device_csr_rw	2.860s	219.792us	1	1	100.00
		spi_device_csr_aliasing	14.800s	3.038ms	1	1	100.00
		spi_device_same_csr_outstanding	3.050s	43.125us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.910s	374.624us	1	1	100.00
		spi_device_tl_intg_err	6.450s	295.054us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.450s	295.054us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	24.130s	19.998ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.8735496765802615369557746699322580560579484622668792858079966651330483666656
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    996344 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[83])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    996344 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    996344 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[979])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.33308053731593854961484363450553119132060825489258157098855254712671931546971
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3316339 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc87bee [110010000111101111101110] vs 0x0 [0])
        UVM_ERROR @   3382339 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7e0ae8 [11111100000101011101000] vs 0x0 [0])
        UVM_ERROR @   3409339 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc71db7 [110001110001110110110111] vs 0x0 [0])
        UVM_ERROR @   3474339 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf25bfb [111100100101101111111011] vs 0x0 [0])
        UVM_ERROR @   3503339 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a9c5e [1010101001110001011110] vs 0x0 [0])