SPI_DEVICE/2P Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	26.630s	20.904ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.190s	204.152us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.870s	105.791us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.120s	2.730ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.340s	663.225us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.460s	192.633us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.870s	105.791us	1	1	100.00
		spi_device_csr_aliasing	6.340s	663.225us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.530s	16.980us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.120s	91.821us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.830s	14.005us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.840s	54.946us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.640s	17.838us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.800s	238.097us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.800s	238.097us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.200s	6.668ms	1	1	100.00
		spi_device_tpm_sts_read	1.800s	62.006us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.840s	360.828us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.390s	1.669ms	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.490s	49.778ms	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.490s	49.778ms	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.400s	204.621us	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.400s	204.621us	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.400s	204.621us	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.400s	204.621us	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.400s	204.621us	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.600s	3.292ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.783m	26.313ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.783m	26.313ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.783m	26.313ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.600s	410.935us	1	1	100.00
		spi_device_read_buffer_direct	7.930s	13.661ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.783m	26.313ms	1	1	100.00
		spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.028m	21.445ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	9.220s	1.302ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	9.220s	1.302ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	26.630s	20.904ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	29.520s	2.286ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.907m	112.432ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.770s	41.951us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.710s	30.780us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.130s	141.776us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.130s	141.776us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.190s	204.152us	1	1	100.00
		spi_device_csr_rw	2.870s	105.791us	1	1	100.00
		spi_device_csr_aliasing	6.340s	663.225us	1	1	100.00
		spi_device_same_csr_outstanding	3.410s	343.607us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.190s	204.152us	1	1	100.00
		spi_device_csr_rw	2.870s	105.791us	1	1	100.00
		spi_device_csr_aliasing	6.340s	663.225us	1	1	100.00
		spi_device_same_csr_outstanding	3.410s	343.607us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.310s	265.933us	1	1	100.00
		spi_device_tl_intg_err	15.780s	4.137ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.780s	4.137ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.004m	111.055ms	1	1	100.00
		TOTAL			33	33	100.00