SPI_HOST Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	26.000s	4.425ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	32.827us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	63.818us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	387.597us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	97.277us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	75.300us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	63.818us	1	1	100.00
		spi_host_csr_aliasing	4.000s	97.277us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	43.974us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	23.261us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	25.898us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	104.437us	1	1	100.00
		spi_host_error_cmd	4.000s	16.916us	1	1	100.00
		spi_host_event	7.000s	170.788us	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	177.624us	1	1	100.00
V2	speed	spi_host_speed	5.000s	177.624us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	177.624us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	17.000s	757.061us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	138.200us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	177.624us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	177.624us	1	1	100.00
V2	duplex	spi_host_smoke	26.000s	4.425ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	26.000s	4.425ms	1	1	100.00
V2	stress_all	spi_host_stress_all	12.000s	1.523ms	1	1	100.00
V2	spien	spi_host_spien	18.000s	2.289ms	1	1	100.00
V2	stall	spi_host_status_stall	1.017m	6.336ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	143.412us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	104.437us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	18.322us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	17.403us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	229.781us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	229.781us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	32.827us	1	1	100.00
		spi_host_csr_rw	4.000s	63.818us	1	1	100.00
		spi_host_csr_aliasing	4.000s	97.277us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	97.378us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	32.827us	1	1	100.00
		spi_host_csr_rw	4.000s	63.818us	1	1	100.00
		spi_host_csr_aliasing	4.000s	97.277us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	97.378us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	100.691us	1	1	100.00
		spi_host_sec_cm	3.000s	179.020us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	100.691us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.000m	3.303ms	1	1	100.00
		TOTAL			26	26	100.00