SRAM_CTRL/MAIN Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	20.030s	1.066ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.490s	66.451us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.500s	29.705us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.820s	99.355us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.460s	27.570us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.750s	1.398ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.500s	29.705us	1	1	100.00
		sram_ctrl_csr_aliasing	1.460s	27.570us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.984m	20.703ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.891m	11.837ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.205m	2.957ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.175m	3.465ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	7.316m	111.638ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	48.960s	2.266ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.330s	8.371ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.704m	27.087ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.510s	2.529ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.968m	14.919ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.160s	1.598ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	13.770s	752.083us	1	1	100.00
		sram_ctrl_throughput_w_readback	7.600s	1.468ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.558m	9.277ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.150s	1.204ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	38.036m	597.254ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.480s	38.314us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.160s	79.992us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.160s	79.992us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.490s	66.451us	1	1	100.00
		sram_ctrl_csr_rw	1.500s	29.705us	1	1	100.00
		sram_ctrl_csr_aliasing	1.460s	27.570us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.420s	17.579us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.490s	66.451us	1	1	100.00
		sram_ctrl_csr_rw	1.500s	29.705us	1	1	100.00
		sram_ctrl_csr_aliasing	1.460s	27.570us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.420s	17.579us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	32.380s	29.325ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.490s	3.430us	0	1	0.00
		sram_ctrl_tl_intg_err	2.800s	326.274us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.490s	3.430us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.800s	326.274us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.558m	9.277ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.558m	9.277ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.500s	29.705us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.704m	27.087ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.704m	27.087ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.704m	27.087ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.330s	8.371ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.260s	1.392ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	32.380s	29.325ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.460s	5.974ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	20.030s	1.066ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	20.030s	1.066ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.704m	27.087ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.490s	3.430us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.330s	8.371ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.490s	3.430us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.490s	3.430us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	20.030s	1.066ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.490s	3.430us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.210s	358.660us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.83373513935619475541073923790041554236043028058384264738835279069394313863796
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 5973996067 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x16) != exp (0x3d)
        UVM_INFO @ 5973996067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.16461854688077979953069653545716711096376156743646700156649426576670060607833
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3430147 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3430147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---