SRAM_CTRL/RET Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.280s	784.621us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	181.641us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.520s	33.938us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.570s	345.486us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	42.227us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.920s	68.060us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.520s	33.938us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	42.227us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.160s	469.734us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.250s	332.364us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.587m	6.475ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.916m	5.326ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	50.890s	13.940ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.383m	1.501ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.170s	107.526us	1	1	100.00
V2	executable	sram_ctrl_executable	8.075m	13.324ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	8.320s	264.982us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.372m	4.859ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	38.470s	1.598ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	30.460s	551.743us	1	1	100.00
		sram_ctrl_throughput_w_readback	25.690s	827.457us	1	1	100.00
V2	regwen	sram_ctrl_regwen	46.270s	14.089ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.520s	104.831us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.978m	105.844ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.540s	30.205us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.450s	572.205us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.450s	572.205us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	181.641us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	33.938us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	42.227us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.750s	86.680us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	181.641us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	33.938us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	42.227us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.750s	86.680us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.370s	760.983us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.470s	3.522us	0	1	0.00
		sram_ctrl_tl_intg_err	2.010s	391.038us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.470s	3.522us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.010s	391.038us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	46.270s	14.089ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	46.270s	14.089ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.520s	33.938us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.075m	13.324ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.075m	13.324ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.075m	13.324ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.170s	107.526us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.850s	130.763us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.370s	760.983us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.890s	137.675us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.280s	784.621us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.280s	784.621us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.075m	13.324ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.470s	3.522us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.170s	107.526us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.470s	3.522us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.470s	3.522us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.280s	784.621us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.470s	3.522us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.869m	1.595ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.87287771708898286687745358269848890772294544678044025296395693166619906505313
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3522374 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3522374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---