SYSRST_CTRL Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.310s 2.129ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.150s 2.483ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.150s 2.427ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.350s 2.359ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 9.440s 4.011ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.320s 2.130ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 4.470m 75.441ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 11.360s 3.172ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 3.330s 2.062ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.320s 2.130ms 1 1 100.00
sysrst_ctrl_csr_aliasing 11.360s 3.172ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 5.336m 176.741ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.801m 55.073ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.920s 3.275ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.560s 3.196ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.670s 2.510ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 5.440s 2.199ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 11.490s 4.630ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.870s 2.635ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 16.270s 761.155ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 22.340s 40.362ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 20.610s 9.396ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.920s 2.043ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 3.000s 2.048ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.720s 2.075ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.720s 2.075ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 9.440s 4.011ms 1 1 100.00
sysrst_ctrl_csr_rw 2.320s 2.130ms 1 1 100.00
sysrst_ctrl_csr_aliasing 11.360s 3.172ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.350s 9.637ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 9.440s 4.011ms 1 1 100.00
sysrst_ctrl_csr_rw 2.320s 2.130ms 1 1 100.00
sysrst_ctrl_csr_aliasing 11.360s 3.172ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.350s 9.637ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 42.300s 22.017ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.383m 42.409ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.383m 42.409ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 9.300s 12.338ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00