UART Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.980s	483.094us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.580s	14.372us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.480s	15.698us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.990s	568.437us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.480s	19.586us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.640s	56.272us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.480s	15.698us	1	1	100.00
		uart_csr_aliasing	1.480s	19.586us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	54.850s	92.159ms	1	1	100.00
V2	parity	uart_smoke	2.980s	483.094us	1	1	100.00
		uart_tx_rx	54.850s	92.159ms	1	1	100.00
V2	parity_error	uart_intr	48.110s	36.780ms	1	1	100.00
		uart_rx_parity_err	54.330s	44.873ms	1	1	100.00
V2	watermark	uart_tx_rx	54.850s	92.159ms	1	1	100.00
		uart_intr	48.110s	36.780ms	1	1	100.00
V2	fifo_full	uart_fifo_full	20.680s	18.830ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.923m	104.178ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	3.176m	195.527ms	1	1	100.00
V2	rx_frame_err	uart_intr	48.110s	36.780ms	1	1	100.00
V2	rx_break_err	uart_intr	48.110s	36.780ms	1	1	100.00
V2	rx_timeout	uart_intr	48.110s	36.780ms	1	1	100.00
V2	perf	uart_perf	4.956m	27.051ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.260s	2.511ms	1	1	100.00
V2	line_loopback	uart_loopback	4.260s	2.511ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	39.780s	234.145ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	13.220s	35.145ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.600s	1.395ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	16.960s	2.939ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.259m	33.443ms	1	1	100.00
V2	stress_all	uart_stress_all	3.889m	123.416ms	1	1	100.00
V2	alert_test	uart_alert_test	1.380s	32.878us	1	1	100.00
V2	intr_test	uart_intr_test	1.490s	20.937us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.150s	29.723us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.150s	29.723us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.580s	14.372us	1	1	100.00
		uart_csr_rw	1.480s	15.698us	1	1	100.00
		uart_csr_aliasing	1.480s	19.586us	1	1	100.00
		uart_same_csr_outstanding	1.490s	47.613us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.580s	14.372us	1	1	100.00
		uart_csr_rw	1.480s	15.698us	1	1	100.00
		uart_csr_aliasing	1.480s	19.586us	1	1	100.00
		uart_same_csr_outstanding	1.490s	47.613us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.580s	245.203us	1	1	100.00
		uart_tl_intg_err	2.020s	347.970us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.020s	347.970us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	27.980s	8.571ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00