CHIP Simulation Results

Monday June 02 2025 18:33:27 UTC

GitHub Revision: `12e45f3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.525m	3.223ms	1	1	100.00
		chip_sw_example_rom	1.397m	2.497ms	1	1	100.00
		chip_sw_example_manufacturer	2.320m	2.737ms	1	1	100.00
		chip_sw_example_concurrency	2.502m	3.067ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.209m	5.909ms	1	1	100.00
V1	csr_rw	chip_csr_rw	4.897m	6.222ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.774m	8.360ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.026h	31.511ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	7.868m	11.216ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.026h	31.511ms	1	1	100.00
		chip_csr_rw	4.897m	6.222ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.380s	42.308us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.700m	3.822ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.700m	3.822ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.700m	3.822ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.960m	4.211ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.960m	4.211ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.763m	4.966ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.424m	3.907ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.524m	3.889ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	24.649m	12.600ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	27.149m	13.143ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	16.872m	13.856ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.946m	4.734ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.946m	4.734ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.014m	3.200ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.131m	3.057ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.340m	3.912ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.643m	2.992ms	1	1	100.00
		chip_tap_straps_testunlock0	3.182m	3.714ms	1	1	100.00
		chip_tap_straps_rma	3.702m	4.678ms	1	1	100.00
		chip_tap_straps_prod	6.199m	7.287ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.635m	2.728ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.132m	9.773ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.470m	5.237ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.470m	5.237ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.245m	7.106ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	22.939m	19.180ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.006m	4.023ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.559m	6.251ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.077m	18.050ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.264m	2.419ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.777m	5.979ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.936m	2.945ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.567m	10.738ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.594m	3.530ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.228m	5.686ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.890m	2.596ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.058m	3.084ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.147m	6.496ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.025m	5.053ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.763m	2.604ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.025m	5.053ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.473m	3.625ms	1	1	100.00
		chip_sw_aes_smoketest	2.434m	3.139ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.063m	2.408ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.040m	2.319ms	1	1	100.00
		chip_sw_csrng_smoketest	2.188m	2.717ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.739m	3.115ms	1	1	100.00
		chip_sw_gpio_smoketest	2.578m	2.664ms	1	1	100.00
		chip_sw_hmac_smoketest	3.008m	3.121ms	1	1	100.00
		chip_sw_kmac_smoketest	2.353m	2.888ms	1	1	100.00
		chip_sw_otbn_smoketest	11.795m	7.329ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.034m	5.360ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.054m	6.607ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.202m	2.263ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.845m	2.629ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.968m	3.338ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.814m	3.272ms	1	1	100.00
		chip_sw_uart_smoketest	2.535m	2.379ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.057m	2.285ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.523m	4.886ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.981h	61.489ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.185m	15.578ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	23.511s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.915m	3.363ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.680m	2.741ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.773h	52.959ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.765h	55.016ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	40.860s	1.959ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	40.860s	1.959ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.026h	31.511ms	1	1	100.00
		chip_same_csr_outstanding	17.892m	14.983ms	1	1	100.00
		chip_csr_hw_reset	3.209m	5.909ms	1	1	100.00
		chip_csr_rw	4.897m	6.222ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.026h	31.511ms	1	1	100.00
		chip_same_csr_outstanding	17.892m	14.983ms	1	1	100.00
		chip_csr_hw_reset	3.209m	5.909ms	1	1	100.00
		chip_csr_rw	4.897m	6.222ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	50.640s	2.516ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.580s	43.508us	1	1	100.00
		xbar_smoke_large_delays	41.540s	6.921ms	1	1	100.00
		xbar_smoke_slow_rsp	1.014m	7.013ms	1	1	100.00
		xbar_random_zero_delays	8.560s	118.618us	1	1	100.00
		xbar_random_large_delays	21.910s	3.274ms	1	1	100.00
		xbar_random_slow_rsp	2.455m	17.639ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	19.770s	266.044us	1	1	100.00
		xbar_error_and_unmapped_addr	15.170s	192.651us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	7.110s	85.797us	1	1	100.00
		xbar_error_and_unmapped_addr	15.170s	192.651us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	18.870s	365.921us	1	1	100.00
		xbar_access_same_device_slow_rsp	25.360s	2.724ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	12.170s	559.523us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.533m	20.799ms	1	1	100.00
		xbar_stress_all_with_error	2.200m	6.774ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.804m	632.683us	1	1	100.00
		xbar_stress_all_with_reset_error	3.246m	7.961ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.185m	15.578ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	30.917m	25.034ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.221m	15.448ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	16.675s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.030s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	15.198s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.776s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	16.447s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.524s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.677s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.853s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.746s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.819s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.586s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.170s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.953s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.855s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.873s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.593s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.894s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.491s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.324s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.463s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.462s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.611s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	21.887s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.103s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.433s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.451s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.511s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.245s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.299s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.222s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	19.390s		0	1	0.00
		rom_e2e_asm_init_dev	13.657s		0	1	0.00
		rom_e2e_asm_init_prod	13.507s		0	1	0.00
		rom_e2e_asm_init_prod_end	15.413s		0	1	0.00
		rom_e2e_asm_init_rma	15.371s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.139m	14.900ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.396m	15.143ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.369m	15.038ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.061m	15.645ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.050m	34.833ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.050m	34.833ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.008m	2.966ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.264m	2.419ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.831m	3.165ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.154m	3.355ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.762m	6.702ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.884m	3.035ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.570m	4.483ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.965m	5.389ms	1	1	100.00
		chip_plic_all_irqs_10	4.594m	3.844ms	1	1	100.00
		chip_plic_all_irqs_20	5.656m	3.943ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.104m	3.204ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.964m	10.006ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.777m	3.531ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.902m	2.103ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.258m	12.397ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.207m	5.738ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.000m	6.363ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.844m	8.233ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.101h	254.720ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.390m	3.448ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.034m	5.360ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.390m	3.448ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.069m	9.834ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.069m	9.834ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.174m	7.444ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.174m	4.638ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.943m	5.906ms	1	1	100.00
		chip_sw_aes_idle	3.154m	3.355ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.378m	3.038ms	1	1	100.00
		chip_sw_kmac_idle	2.617m	3.274ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.560m	5.279ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.161m	4.586ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.560m	4.362ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.414m	3.891ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.425m	11.951ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.413m	4.020ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.627m	4.857ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.743m	4.838ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.170m	4.399ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.879m	3.469ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.061m	4.678ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.245m	7.106ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.617m	5.398ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.743m	4.838ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.170m	4.399ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.006m	4.023ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.559m	6.251ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.077m	18.050ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.264m	2.419ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.777m	5.979ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.936m	2.945ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.567m	10.738ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.594m	3.530ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.228m	5.686ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.890m	2.596ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.816m	3.166ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.153m	5.459ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.689m	7.013ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	45.120m	24.755ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.268m	2.505ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.498m	2.846ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.414m	13.195ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.807m	3.323ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.376m	4.668ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.269m	19.042ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	43.893m	32.291ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.245m	7.106ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.138m	4.373ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.399m	3.573ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	12.207m	5.738ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.827m	7.072ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.749m	2.806ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.197m	6.786ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.798m	2.889ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	56.342m	27.026ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.430m	2.801ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.202m	7.345ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.430m	2.801ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.827m	7.072ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.421m	2.851ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.346m	19.549ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.828m	5.551ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.559m	6.251ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.203m	3.538ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.006m	4.023ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	50.722m	43.293ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.346m	19.549ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.611m	3.403ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.837m	10.634ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.119m	5.605ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	50.722m	43.293ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.119m	5.605ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.119m	5.605ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.119m	5.605ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.119m	5.605ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.516m	4.053ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.887m	4.786ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.117m	5.674ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.117m	5.674ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.258m	2.571ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.936m	2.945ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.378m	3.038ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.325m	3.404ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.970m	3.351ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.257m	4.781ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.128m	4.695ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.080m	5.512ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.267m	3.992ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.837m	10.634ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.567m	10.738ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	18.733m	9.462ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.762m	6.702ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	31.422m	11.087ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.109m	2.899ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.933m	2.769ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.594m	3.530ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.837m	10.634ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.852m	2.420ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.928m	8.676ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.617m	3.274ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.570m	4.483ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.643m	2.992ms	1	1	100.00
		chip_tap_straps_rma	3.702m	4.678ms	1	1	100.00
		chip_tap_straps_prod	6.199m	7.287ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.460m	3.109ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	24.412m	11.830ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.119m	5.605ms	1	1	100.00
		chip_sw_flash_rma_unlocked	50.722m	43.293ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.225m	2.944ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.008m	6.834ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.268m	6.272ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.035m	6.605ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.837m	10.634ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.213m	9.421ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.604m	8.489ms	1	1	100.00
		chip_prim_tl_access	1.516m	4.053ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.617m	5.398ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.413m	4.020ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.627m	4.857ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.743m	4.838ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.170m	4.399ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.879m	3.469ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.061m	4.678ms	1	1	100.00
		chip_tap_straps_dev	1.643m	2.992ms	1	1	100.00
		chip_tap_straps_rma	3.702m	4.678ms	1	1	100.00
		chip_tap_straps_prod	6.199m	7.287ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.557m	10.043ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.996m	4.556ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.371m	2.882ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.375m	2.500ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.498m	3.296ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.757m	27.347ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.557m	10.043ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	57.434m	48.339ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.046h	46.268ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.659m	10.954ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	53.385m	47.642ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	17.757m	27.347ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.316m	2.780ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.303m	3.018ms	1	1	100.00
		rom_volatile_raw_unlock	14.333s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	48.368m	17.163ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.077m	18.050ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.943m	5.906ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.943m	5.906ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.943m	5.906ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.684m	3.605ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.346m	19.549ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.684m	3.605ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.837m	10.634ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.328m	5.068ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.551m	3.366ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.346m	19.549ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.684m	3.605ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.837m	10.634ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.328m	5.068ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.551m	3.366ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.931m	5.441ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.460m	3.109ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.225m	2.944ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.008m	6.834ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.268m	6.272ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.035m	6.605ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.206m	5.052ms	1	1	100.00
		chip_prim_tl_access	1.516m	4.053ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.516m	4.053ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.261m	8.424ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.905m	5.575ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.181m	22.531ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.521m	7.313ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.672m	10.408ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.210m	5.969ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.280m	23.404ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.149m	15.225ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.069m	9.834ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.818m	12.440ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.831m	5.419ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.905m	5.575ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.285m	4.950ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.178m	42.670ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.253m	7.024ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.622m	4.225ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.521m	24.426ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.135m	8.917ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	10.666m	11.542ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.374m	24.134ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.516m	2.849ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.213m	9.421ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.213m	9.421ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	10.666m	11.542ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.521m	24.426ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.831m	5.419ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.034m	5.360ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.063m	4.331ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.671m	5.108ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.060m	4.118ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.964m	10.006ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.444m	2.810ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.000m	6.363ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.647m	4.096ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.098m	4.603ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.832m	3.109ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.551m	3.366ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.671m	5.108ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.671m	5.108ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.375m	12.320ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.951m	14.021ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.063m	4.331ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.774m	4.922ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.705m	5.643ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.702m	4.678ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.557m	10.043ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.965m	5.389ms	1	1	100.00
		chip_plic_all_irqs_10	4.594m	3.844ms	1	1	100.00
		chip_plic_all_irqs_20	5.656m	3.943ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.827m	3.350ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.269m	2.281ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.185m	15.578ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.353m	7.539ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.936m	3.258ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.226m	2.930ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.230m	2.600ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.328m	5.068ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.228m	5.686ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.312m	8.195ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.499m	8.362ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.604m	8.489ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.470m	5.237ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.135m	8.917ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.883m	22.035ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.793m	2.342ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.886m	3.454ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.094m	4.386ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.883m	22.035ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.883m	22.035ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.155m	10.731ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.155m	10.731ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.655m	5.909ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.050m	34.833ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.369m	3.411ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.644m	3.320ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.741m	4.502ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.509m	4.372ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.965m	7.333ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.259h	31.809ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.040m	11.780ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.434m	2.285ms	1	1	100.00
V2		TOTAL			228	275	82.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.886m	3.054ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.296m	2.441ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.273h	71.426ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.561m	5.210ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.426m	11.699ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.116m	11.018ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.369m	10.532ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	55.702s		0	1	0.00
		rom_e2e_jtag_inject_dev	47.687s		0	1	0.00
		rom_e2e_jtag_inject_rma	38.873s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.325s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.768m	5.441ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.967m	3.110ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.853m	6.536ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	20.085m	9.413ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.651m	2.730ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.040m	4.667ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.224m	2.548ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.946m	4.987ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.212m	5.583ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.498m	4.002ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	10.666m	11.542ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.426m	11.699ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.116m	11.018ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.369m	10.532ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.154m	5.285ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.424m	6.627ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.274h	38.588ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.274h	38.588ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.682m	3.548ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.960m	4.211ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.965m	18.744ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	3.453m	3.406ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.569m	4.477ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.046m	2.862ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.599m	3.154ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.474m	3.997ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.953s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.245m	3.084ms	1	1	100.00
		TOTAL			273	325	84.00

Failure Buckets

Job returned non-zero exit code has 42 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.39325202330755039471533697449546530368869412559832437825670630265403527291981
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 3.034s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.39697030581348090070533780382520215711222282905821860606243165020034093771475
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 4.330s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.105209660370851946163958883632120027521455362496682075425219112298901275683134
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26284 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.881s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.89202581919056186437380528800546359448687326543999880840766192790052038447293
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26284 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.028s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.74950048390226535927524979857754798006032439134501010505607017063061035687075
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26284 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 3.105s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 37 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.103362881208580843606120265474419336733619428727357483423991520968488278213551
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3258.070546 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3258.070546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@112755) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.46682117393987294923886178160300219416549644209358896693259698174852877563030
Line 448, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5108.185852 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@112755) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5108.185852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.32321325770086495910424180076183919435125353282666345269042437045772846620298
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10731.015920 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10731.015920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.93212064775233223946897480132189935939516759090023999273247193262249344516167
    Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34832.603517 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34832.603517 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.54257237243010714455202859760475050843529072737536298980455508869295604960390
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3035.189400 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3035.189400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.77118101347099885457120317552376414673406164410749363687648137873173691239991
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2102.643824 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2102.643824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.12096100577616048760305309555037625690827539962248382716585022598692341712398
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2805.695671 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2805.695671 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34339) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.7212859846521003392066602434002141949337822957761852861736144121779340185615
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1958.797880 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34339) { a_addr: 'h107c4  a_data: 'he95ac01b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h18d1e  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1958.797880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.46451167107390089684144939111377938981382572632795657553135220602835092648324
    Line 426, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3362.640000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3362.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.22031346778651159604129904997590131998379564343979347620665795221498081135606
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2740.947500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2740.947500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```