ADC_CTRL Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	12.240s	5.724ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.040s	871.454us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.200s	416.549us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	27.190s	40.652ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.030s	963.316us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.150s	356.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.200s	416.549us	1	1	100.00
		adc_ctrl_csr_aliasing	4.030s	963.316us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.752m	166.904ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.112m	159.298ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	6.670m	490.673ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.179m	162.379ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	10.207m	360.964ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	11.130m	401.709ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	6.517m	497.355ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	6.975m	355.055ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.390s	4.819ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	7.470s	44.462ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.622m	94.084ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	13.096m	488.615ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.930s	279.442us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.410s	519.339us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.400s	836.965us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.400s	836.965us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.040s	871.454us	1	1	100.00
		adc_ctrl_csr_rw	2.200s	416.549us	1	1	100.00
		adc_ctrl_csr_aliasing	4.030s	963.316us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.930s	2.234ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.040s	871.454us	1	1	100.00
		adc_ctrl_csr_rw	2.200s	416.549us	1	1	100.00
		adc_ctrl_csr_aliasing	4.030s	963.316us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.930s	2.234ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.740s	8.321ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.010s	8.153ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.010s	8.153ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.320s	37.051ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00