EDN Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.760s 44.354us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.510s 35.839us 1 1 100.00
V1 csr_rw edn_csr_rw 1.700s 26.330us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.080s 320.704us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.010s 47.734us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.710s 37.520us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.700s 26.330us 1 1 100.00
edn_csr_aliasing 2.010s 47.734us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.390s 114.367us 1 1 100.00
V2 csrng_commands edn_genbits 2.390s 114.367us 1 1 100.00
V2 genbits edn_genbits 2.390s 114.367us 1 1 100.00
V2 interrupts edn_intr 1.670s 26.055us 1 1 100.00
V2 alerts edn_alert 1.950s 22.273us 1 1 100.00
V2 errs edn_err 1.770s 23.266us 1 1 100.00
V2 disable edn_disable 1.790s 159.534us 1 1 100.00
edn_disable_auto_req_mode 1.830s 133.661us 1 1 100.00
V2 stress_all edn_stress_all 6.310s 413.621us 1 1 100.00
V2 intr_test edn_intr_test 1.610s 11.174us 1 1 100.00
V2 alert_test edn_alert_test 1.770s 38.231us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.900s 317.998us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.900s 317.998us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.510s 35.839us 1 1 100.00
edn_csr_rw 1.700s 26.330us 1 1 100.00
edn_csr_aliasing 2.010s 47.734us 1 1 100.00
edn_same_csr_outstanding 1.930s 42.006us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.510s 35.839us 1 1 100.00
edn_csr_rw 1.700s 26.330us 1 1 100.00
edn_csr_aliasing 2.010s 47.734us 1 1 100.00
edn_same_csr_outstanding 1.930s 42.006us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 3.950s 964.902us 1 1 100.00
edn_tl_intg_err 2.820s 221.075us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.800s 19.035us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.950s 22.273us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 3.950s 964.902us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 3.950s 964.902us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 3.950s 964.902us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 3.950s 964.902us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.950s 22.273us 1 1 100.00
edn_sec_cm 3.950s 964.902us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.950s 22.273us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.820s 221.075us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets