HMAC Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.940s 1.113ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.790s 31.322us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.830s 136.801us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.380s 705.300us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.260s 616.815us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.870s 23.110us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.830s 136.801us 1 1 100.00
hmac_csr_aliasing 6.260s 616.815us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 20.280s 8.635ms 1 1 100.00
V2 back_pressure hmac_back_pressure 55.280s 1.382ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.560s 680.774us 1 1 100.00
hmac_test_sha384_vectors 6.000m 48.147ms 1 1 100.00
hmac_test_sha512_vectors 6.173m 14.085ms 1 1 100.00
hmac_test_hmac256_vectors 6.430s 195.387us 1 1 100.00
hmac_test_hmac384_vectors 8.320s 1.094ms 1 1 100.00
hmac_test_hmac512_vectors 8.930s 267.849us 1 1 100.00
V2 burst_wr hmac_burst_wr 23.280s 3.188ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.921m 2.541ms 1 1 100.00
V2 error hmac_error 38.050s 3.210ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.334m 25.385ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.940s 1.113ms 1 1 100.00
hmac_long_msg 20.280s 8.635ms 1 1 100.00
hmac_back_pressure 55.280s 1.382ms 1 1 100.00
hmac_datapath_stress 4.921m 2.541ms 1 1 100.00
hmac_burst_wr 23.280s 3.188ms 1 1 100.00
hmac_stress_all 1.435m 2.462ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.940s 1.113ms 1 1 100.00
hmac_long_msg 20.280s 8.635ms 1 1 100.00
hmac_back_pressure 55.280s 1.382ms 1 1 100.00
hmac_datapath_stress 4.921m 2.541ms 1 1 100.00
hmac_wipe_secret 1.334m 25.385ms 1 1 100.00
hmac_test_sha256_vectors 8.560s 680.774us 1 1 100.00
hmac_test_sha384_vectors 6.000m 48.147ms 1 1 100.00
hmac_test_sha512_vectors 6.173m 14.085ms 1 1 100.00
hmac_test_hmac256_vectors 6.430s 195.387us 1 1 100.00
hmac_test_hmac384_vectors 8.320s 1.094ms 1 1 100.00
hmac_test_hmac512_vectors 8.930s 267.849us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.940s 1.113ms 1 1 100.00
hmac_long_msg 20.280s 8.635ms 1 1 100.00
hmac_back_pressure 55.280s 1.382ms 1 1 100.00
hmac_datapath_stress 4.921m 2.541ms 1 1 100.00
hmac_burst_wr 23.280s 3.188ms 1 1 100.00
hmac_error 38.050s 3.210ms 1 1 100.00
hmac_wipe_secret 1.334m 25.385ms 1 1 100.00
hmac_test_sha256_vectors 8.560s 680.774us 1 1 100.00
hmac_test_sha384_vectors 6.000m 48.147ms 1 1 100.00
hmac_test_sha512_vectors 6.173m 14.085ms 1 1 100.00
hmac_test_hmac256_vectors 6.430s 195.387us 1 1 100.00
hmac_test_hmac384_vectors 8.320s 1.094ms 1 1 100.00
hmac_test_hmac512_vectors 8.930s 267.849us 1 1 100.00
hmac_stress_all 1.435m 2.462ms 1 1 100.00
V2 stress_all hmac_stress_all 1.435m 2.462ms 1 1 100.00
V2 alert_test hmac_alert_test 1.550s 83.303us 1 1 100.00
V2 intr_test hmac_intr_test 1.620s 37.403us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.920s 662.195us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.920s 662.195us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.790s 31.322us 1 1 100.00
hmac_csr_rw 1.830s 136.801us 1 1 100.00
hmac_csr_aliasing 6.260s 616.815us 1 1 100.00
hmac_same_csr_outstanding 2.240s 989.086us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.790s 31.322us 1 1 100.00
hmac_csr_rw 1.830s 136.801us 1 1 100.00
hmac_csr_aliasing 6.260s 616.815us 1 1 100.00
hmac_same_csr_outstanding 2.240s 989.086us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.810s 343.411us 1 1 100.00
hmac_tl_intg_err 2.340s 358.598us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.340s 358.598us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.940s 1.113ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.730s 30.916us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 51.600s 4.159ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.820s 449.922us 1 1 100.00
TOTAL 28 28 100.00