I2C Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	55.880s	5.307ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.730s	1.415ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.640s	17.681us	1	1	100.00
V1	csr_rw	i2c_csr_rw	5.700s	6.133ms	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.130s	117.842us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.880s	71.387us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.890s	154.160us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	5.700s	6.133ms	1	1	100.00
		i2c_csr_aliasing	1.880s	71.387us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.030s	272.862us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	20.651m	20.023ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.127m	2.397ms	1	1	100.00
V2	host_override	i2c_host_override	1.570s	22.307us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.378m	5.789ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	33.550s	4.073ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.440s	153.667us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.050s	834.230us	1	1	100.00
		i2c_host_fifo_reset_rx	7.740s	162.615us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.174m	3.480ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	13.930s	2.878ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.870s	44.805us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.200s	2.308ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	4.122m	24.418ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.860s	1.118ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	20.580s	620.426us	1	1	100.00
		i2c_target_intr_smoke	7.310s	7.182ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.790s	278.536us	1	1	100.00
		i2c_target_fifo_reset_tx	1.650s	131.436us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.900s	13.412ms	1	1	100.00
		i2c_target_stress_rd	20.580s	620.426us	1	1	100.00
		i2c_target_intr_stress_wr	13.490s	2.744ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.830s	1.329ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.700s	2.101ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.980s	2.911ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.730s	10.603ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.320s	133.943us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.570s	158.240us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.127m	2.397ms	1	1	100.00
		i2c_host_perf_precise	10.590s	2.478ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	13.930s	2.878ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.140s	404.506us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.810s	509.449us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.880s	540.681us	1	1	100.00
		i2c_target_nack_txstretch	2.240s	2.161ms	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.260s	1.716ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.730s	1.314ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.800s	17.013us	1	1	100.00
V2	intr_test	i2c_intr_test	1.640s	32.777us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.090s	285.148us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.090s	285.148us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.640s	17.681us	1	1	100.00
		i2c_csr_rw	5.700s	6.133ms	1	1	100.00
		i2c_csr_aliasing	1.880s	71.387us	1	1	100.00
		i2c_same_csr_outstanding	1.750s	37.145us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.640s	17.681us	1	1	100.00
		i2c_csr_rw	5.700s	6.133ms	1	1	100.00
		i2c_csr_aliasing	1.880s	71.387us	1	1	100.00
		i2c_same_csr_outstanding	1.750s	37.145us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.230s	71.593us	1	1	100.00
		i2c_sec_cm	1.710s	165.989us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.230s	71.593us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	13.730s	1.735ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.920s	704.085us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	26.440s	971.831us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.99677017007112607095633570442396706760683106561905370951672674084923079176735
      Line 139, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 20022719276 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @23887438
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.36036995768118053315942252537272773352834650407274384362402859392144741153982
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 704085311 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 123 [0x7b])
        UVM_INFO @ 704085311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.33571775527434267015448158853874495585136218865216361627641809526220969088329
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10602702352 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10602702352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.92476516579694527562332151866229789299228185642056305432436365242594525455355
      Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1734887872 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1734887872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.39743859320274213816780225290898261034062953072462948974917519503651214747812
      Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 971831455 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 971831455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.91147842358623948256671441664268539706277900413554863216660362582419117690864
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  44804550 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.83177738823252906968793049709575224697954402056233290281921889297942233988370
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 2160772741 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 2160772741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---