KEYMGR Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: `891c607`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.470s	60.123us	1	1	100.00
V1	random	keymgr_random	4.660s	159.705us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.740s	15.464us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.030s	102.267us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.410s	431.866us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.620s	514.816us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.920s	81.306us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.030s	102.267us	1	1	100.00
		keymgr_csr_aliasing	8.620s	514.816us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	20.830s	2.163ms	1	1	100.00
V2	sideload	keymgr_sideload	2.340s	64.032us	1	1	100.00
		keymgr_sideload_kmac	2.830s	92.080us	1	1	100.00
		keymgr_sideload_aes	3.380s	61.560us	1	1	100.00
		keymgr_sideload_otbn	20.500s	3.043ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.930s	61.849us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.720s	340.414us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.780s	129.891us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.900s	336.159us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.510s	180.036us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	9.540s	589.335us	1	1	100.00
V2	stress_all	keymgr_stress_all	29.110s	4.300ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.540s	11.456us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.650s	28.956us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.360s	27.348us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.360s	27.348us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.740s	15.464us	1	1	100.00
		keymgr_csr_rw	2.030s	102.267us	1	1	100.00
		keymgr_csr_aliasing	8.620s	514.816us	1	1	100.00
		keymgr_same_csr_outstanding	1.610s	20.705us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.740s	15.464us	1	1	100.00
		keymgr_csr_rw	2.030s	102.267us	1	1	100.00
		keymgr_csr_aliasing	8.620s	514.816us	1	1	100.00
		keymgr_same_csr_outstanding	1.610s	20.705us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
		keymgr_tl_intg_err	1.720s	13.773us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.750s	872.279us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.750s	872.279us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.750s	872.279us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.750s	872.279us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	3.850s	103.495us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.720s	13.773us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.750s	872.279us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	20.830s	2.163ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.660s	159.705us	1	1	100.00
		keymgr_csr_rw	2.030s	102.267us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.660s	159.705us	1	1	100.00
		keymgr_csr_rw	2.030s	102.267us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.660s	159.705us	1	1	100.00
		keymgr_csr_rw	2.030s	102.267us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.720s	340.414us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.510s	180.036us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.510s	180.036us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.660s	159.705us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.210s	177.821us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.940s	64.114us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.720s	340.414us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.940s	64.114us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.940s	64.114us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.940s	64.114us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.810s	2.810ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.940s	64.114us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.320s	335.931us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_tl_intg_err has 1 failures.

0.keymgr_tl_intg_err.76220458081417305255813908604769690053573631475907498893627857456773158303643
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  13772838 ps: (keymgr_csr_assert_fpv.sv:434) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  13772838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 1 failures.

0.keymgr_same_csr_outstanding.106427828360291342110811710870561606561441242958754383765800722616983894682507
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  20704893 ps: (keymgr_csr_assert_fpv.sv:404) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  20704893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.54709556790025979998550187375490275025835603960865183186178381668690006771958
    Line 845, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 335930988 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 335930988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```