KMAC/MASKED Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	38.840s	1.318ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	19.868us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.650s	32.535us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.560s	615.616us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.140s	679.764us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.230s	171.025us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.650s	32.535us	1	1	100.00
		kmac_csr_aliasing	6.140s	679.764us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	14.930us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	19.210us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.164m	199.940ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.140m	16.689ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.838m	80.314ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.930s	2.221ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.935m	94.306ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.198m	162.211ms	1	1	100.00
		kmac_test_vectors_shake_128	2.318m	7.360ms	1	1	100.00
		kmac_test_vectors_shake_256	1.841m	7.117ms	1	1	100.00
		kmac_test_vectors_kmac	3.720s	489.490us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.850s	63.251us	1	1	100.00
V2	sideload	kmac_sideload	5.021m	18.643ms	1	1	100.00
V2	app	kmac_app	3.186m	9.371ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	53.230s	20.282ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.182m	15.055ms	1	1	100.00
V2	error	kmac_error	50.000s	942.187us	1	1	100.00
V2	key_error	kmac_key_error	10.870s	5.338ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.600s	68.075us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.620s	21.280us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.780s	21.891us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.290s	8.457ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.890s	98.208us	1	1	100.00
V2	stress_all	kmac_stress_all	12.027m	50.349ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	23.509us	1	1	100.00
V2	alert_test	kmac_alert_test	1.510s	16.614us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.960s	115.772us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.960s	115.772us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	19.868us	1	1	100.00
		kmac_csr_rw	1.650s	32.535us	1	1	100.00
		kmac_csr_aliasing	6.140s	679.764us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	172.717us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	19.868us	1	1	100.00
		kmac_csr_rw	1.650s	32.535us	1	1	100.00
		kmac_csr_aliasing	6.140s	679.764us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	172.717us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.630s	166.486us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.630s	166.486us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.630s	166.486us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.630s	166.486us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.740s	41.689us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.580s	9.475ms	1	1	100.00
		kmac_tl_intg_err	1.840s	39.087us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.840s	39.087us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.890s	98.208us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	38.840s	1.318ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.021m	18.643ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.630s	166.486us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.580s	9.475ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.580s	9.475ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.580s	9.475ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	38.840s	1.318ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.890s	98.208us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.580s	9.475ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.164m	3.970ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	38.840s	1.318ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.040s	21.936us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.14965545127610942771822941036511521564032005321227856595120662770205213338338
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  41688537 ps: (kmac_csr_assert_fpv.sv:510) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  41688537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.48004034456321197160368374576193831905905678918548823628021566779448011495692
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @  39087135 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @  39087135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.59741882403355466050126800063782424693436414801085524033021223567120189389879
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  21936203 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @  21936203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---