KMAC/UNMASKED Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	7.330s	2.104ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	21.814us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	16.251us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.180s	6.043ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.120s	198.490us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	171.536us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	16.251us	1	1	100.00
		kmac_csr_aliasing	5.120s	198.490us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	22.571us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.040s	18.692us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	22.609m	295.992ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.175m	5.258ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.900m	40.044ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.260s	1.918ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.625m	215.470ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.207m	41.672ms	1	1	100.00
		kmac_test_vectors_shake_128	1.983m	17.866ms	1	1	100.00
		kmac_test_vectors_shake_256	1.415m	6.330ms	1	1	100.00
		kmac_test_vectors_kmac	2.390s	28.930us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.330s	207.890us	1	1	100.00
V2	sideload	kmac_sideload	57.480s	3.979ms	1	1	100.00
V2	app	kmac_app	1.562m	6.366ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.446m	7.883ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.332m	72.780ms	1	1	100.00
V2	error	kmac_error	25.320s	1.198ms	1	1	100.00
V2	key_error	kmac_key_error	4.780s	1.880ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.690s	166.637us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.870s	23.335us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	3.380s	270.731us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	9.610s	4.015ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.870s	95.413us	1	1	100.00
V2	stress_all	kmac_stress_all	54.260s	8.708ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.590s	15.816us	1	1	100.00
V2	alert_test	kmac_alert_test	1.550s	14.870us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.480s	304.990us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.480s	304.990us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	21.814us	1	1	100.00
		kmac_csr_rw	1.710s	16.251us	1	1	100.00
		kmac_csr_aliasing	5.120s	198.490us	1	1	100.00
		kmac_same_csr_outstanding	2.660s	161.427us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	21.814us	1	1	100.00
		kmac_csr_rw	1.710s	16.251us	1	1	100.00
		kmac_csr_aliasing	5.120s	198.490us	1	1	100.00
		kmac_same_csr_outstanding	2.660s	161.427us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.210s	141.301us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.210s	141.301us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.210s	141.301us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.210s	141.301us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.590s	1.348ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	48.590s	21.623ms	1	1	100.00
		kmac_tl_intg_err	3.760s	376.768us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.760s	376.768us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.870s	95.413us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	7.330s	2.104ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	57.480s	3.979ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.210s	141.301us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.590s	21.623ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.590s	21.623ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.590s	21.623ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	7.330s	2.104ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.870s	95.413us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.590s	21.623ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.950m	3.301ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	7.330s	2.104ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.173m	11.869ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.79219254798782644600794989318971872512503940331317412206633436642978318557417
      Line 199, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11868643216 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 11868643216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---