ROM_CTRL/32KB Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.480s 323.156us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.150s 487.213us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.920s 1.050ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.010s 386.969us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.870s 169.360us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.180s 156.553us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.920s 1.050ms 1 1 100.00
rom_ctrl_csr_aliasing 4.870s 169.360us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.110s 774.755us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.650s 632.230us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.670s 228.570us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.710s 581.103us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.450s 840.991us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.460s 811.043us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.190s 290.178us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.190s 290.178us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.150s 487.213us 1 1 100.00
rom_ctrl_csr_rw 5.920s 1.050ms 1 1 100.00
rom_ctrl_csr_aliasing 4.870s 169.360us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.050s 169.042us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.150s 487.213us 1 1 100.00
rom_ctrl_csr_rw 5.920s 1.050ms 1 1 100.00
rom_ctrl_csr_aliasing 4.870s 169.360us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.050s 169.042us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 15.530s 566.942us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.998m 1.938ms 1 1 100.00
rom_ctrl_tl_intg_err 23.070s 248.935us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.998m 1.938ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.998m 1.938ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.998m 1.938ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.998m 1.938ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.480s 323.156us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.480s 323.156us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.480s 323.156us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.070s 248.935us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.450s 840.991us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 47.000s 12.951ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 15.530s 566.942us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.998m 1.938ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.277m 11.218ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00