ROM_CTRL/64KB Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.460s 223.948us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.340s 5.017ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.890s 212.528us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.920s 956.157us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.030s 957.399us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.420s 240.132us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.890s 212.528us 1 1 100.00
rom_ctrl_csr_aliasing 7.030s 957.399us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.550s 296.476us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.970s 260.513us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.280s 219.382us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.010s 3.104ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.310s 1.622ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.030s 480.125us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.410s 2.393ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.410s 2.393ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.340s 5.017ms 1 1 100.00
rom_ctrl_csr_rw 7.890s 212.528us 1 1 100.00
rom_ctrl_csr_aliasing 7.030s 957.399us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.890s 378.484us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.340s 5.017ms 1 1 100.00
rom_ctrl_csr_rw 7.890s 212.528us 1 1 100.00
rom_ctrl_csr_aliasing 7.030s 957.399us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.890s 378.484us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 38.300s 2.253ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.534m 922.241us 1 1 100.00
rom_ctrl_tl_intg_err 1.118m 1.255ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.534m 922.241us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.534m 922.241us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.534m 922.241us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.534m 922.241us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.460s 223.948us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.460s 223.948us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.460s 223.948us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.118m 1.255ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.310s 1.622ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.611m 65.079ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 38.300s 2.253ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.534m 922.241us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.214m 29.427ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00