RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 11.230s 10.129ms 0 1 0.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.790s 1.427ms 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.600s 151.817us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 6.510s 5.999ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.180s 995.521us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.720s 5.532ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 11.260s 5.252ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 6.440s 2.607ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 16.480s 15.532ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.800s 296.689us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.770s 206.757us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.610s 201.344us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.540s 102.577us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.590s 121.148us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.850s 679.677us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.760s 215.151us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.270s 1.326ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.800s 296.689us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.020s 483.737us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.720s 531.821us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.610s 201.344us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.640s 84.431us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.190s 257.823us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.180s 158.635us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 19.720s 7.047ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 48.600s 13.375ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.200s 74.898us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 48.600s 13.375ms 1 1 100.00
rv_dm_csr_rw 2.180s 158.635us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.670s 70.216us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.630s 44.750us 1 1 100.00
V1 TOTAL 25 27 92.59
V2 idcode rv_dm_smoke 11.230s 10.129ms 0 1 0.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.840s 664.597us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.650s 183.443us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.950s 532.502us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.800s 927.290us 1 1 100.00
V2 sba rv_dm_sba_tl_access 7.190s 5.614ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.970s 314.516us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.070s 2.628ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 7.910s 12.999ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.820s 693.408us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.760s 615.769us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.690s 92.340us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.570s 140.092us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 26.250s 13.689ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.580s 79.098us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.640s 63.586us 1 1 100.00
V2 stress_all rv_dm_stress_all 2.750s 2.350ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.530s 176.910us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 3.310s 498.205us 1 1 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 3.310s 498.205us 1 1 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 48.600s 13.375ms 1 1 100.00
rv_dm_csr_hw_reset 2.190s 257.823us 1 1 100.00
rv_dm_csr_rw 2.180s 158.635us 1 1 100.00
rv_dm_same_csr_outstanding 6.590s 948.575us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 48.600s 13.375ms 1 1 100.00
rv_dm_csr_hw_reset 2.190s 257.823us 1 1 100.00
rv_dm_csr_rw 2.180s 158.635us 1 1 100.00
rv_dm_same_csr_outstanding 6.590s 948.575us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 2.680s 1.031ms 1 1 100.00
rv_dm_tl_intg_err 10.710s 1.848ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 10.710s 1.848ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.760s 615.769us 1 1 100.00
rv_dm_debug_disabled 1.530s 166.225us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.760s 615.769us 1 1 100.00
rv_dm_debug_disabled 1.530s 166.225us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 11.230s 10.129ms 0 1 0.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.300s 316.769us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.000s 263.538us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.000s 263.538us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.300s 316.769us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.020s 106.723us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.570s 24.789us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets