RV_TIMER Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.540s	12.790us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.620s	45.952us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.640s	18.255us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.210s	295.516us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.880s	145.790us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.540s	49.197us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.640s	18.255us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	145.790us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.490s	71.749us	1	1	100.00
V2	disabled	rv_timer_disabled	2.390s	338.941us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	37.560s	34.579ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	37.560s	34.579ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.540s	665.096us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.430s	38.376us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.500s	17.853us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.980s	140.343us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.980s	140.343us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.620s	45.952us	1	1	100.00
		rv_timer_csr_rw	1.640s	18.255us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	145.790us	1	1	100.00
		rv_timer_same_csr_outstanding	1.500s	80.592us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.620s	45.952us	1	1	100.00
		rv_timer_csr_rw	1.640s	18.255us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	145.790us	1	1	100.00
		rv_timer_same_csr_outstanding	1.500s	80.592us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.790s	82.931us	1	1	100.00
		rv_timer_tl_intg_err	1.870s	94.670us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.870s	94.670us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	25.170s	34.487ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.430s	176.432us	1	1	100.00
		rv_timer_max	1.510s	156.141us	1	1	100.00
		TOTAL			19	19	100.00