SPI_DEVICE/1R1W Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.217m	14.081ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.720s	35.581us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.290s	33.825us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.560s	526.844us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.380s	110.196us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.600s	158.141us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.290s	33.825us	1	1	100.00
		spi_device_csr_aliasing	6.380s	110.196us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.610s	12.473us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.940s	18.694us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	43.892us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.760s	1.827us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.940s	7.197us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.940s	96.030us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.940s	96.030us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.110s	338.374us	1	1	100.00
		spi_device_tpm_sts_read	1.690s	116.365us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.050s	11.383ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.950s	2.561ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.650s	1.748ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.650s	1.748ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.780s	1.191ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.780s	1.191ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.780s	1.191ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.780s	1.191ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.780s	1.191ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.200s	441.497us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.610s	1.287ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.610s	1.287ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.610s	1.287ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.670s	276.298us	1	1	100.00
		spi_device_read_buffer_direct	4.300s	680.837us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.610s	1.287ms	1	1	100.00
		spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	34.150s	2.741ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.500s	831.990us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.500s	831.990us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.217m	14.081ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	25.640s	16.950ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.980s	188.805us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.860s	15.070us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.820s	71.068us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.580s	77.495us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.580s	77.495us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.720s	35.581us	1	1	100.00
		spi_device_csr_rw	2.290s	33.825us	1	1	100.00
		spi_device_csr_aliasing	6.380s	110.196us	1	1	100.00
		spi_device_same_csr_outstanding	3.930s	62.935us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.720s	35.581us	1	1	100.00
		spi_device_csr_rw	2.290s	33.825us	1	1	100.00
		spi_device_csr_aliasing	6.380s	110.196us	1	1	100.00
		spi_device_same_csr_outstanding	3.930s	62.935us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.960s	38.411us	1	1	100.00
		spi_device_tl_intg_err	5.950s	715.780us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.950s	715.780us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.140s	6.022ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.90164937312653603959251674289357284855067813069684287646278592928907642712785
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1569866 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[32])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1569866 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1569866 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[928])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9097992835345091468176557018535713461439317962185509744354051102198880408329
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4654966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4cbc96 [10011001011110010010110] vs 0x0 [0])
        UVM_ERROR @   4680966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41dfcf [10000011101111111001111] vs 0x0 [0])
        UVM_ERROR @   4695966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9bb9a3 [100110111011100110100011] vs 0x0 [0])
        UVM_ERROR @   4762966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f717c [1011110111000101111100] vs 0x0 [0])
        UVM_ERROR @   4850966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5313a3 [10100110001001110100011] vs 0x0 [0])