| V1 |
smoke |
spi_device_flash_and_tpm |
48.480s |
5.384ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_device_csr_hw_reset |
1.860s |
60.029us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_device_csr_rw |
1.900s |
71.162us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_device_csr_bit_bash |
10.330s |
935.012us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_device_csr_aliasing |
16.940s |
4.451ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_device_csr_mem_rw_with_rand_reset |
3.100s |
222.514us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_device_csr_rw |
1.900s |
71.162us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
16.940s |
4.451ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_device_mem_walk |
1.520s |
17.349us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_device_mem_partial_access |
2.270s |
194.104us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
csb_read |
spi_device_csb_read |
1.810s |
34.650us |
1 |
1 |
100.00 |
| V2 |
mem_parity |
spi_device_mem_parity |
2.060s |
27.470us |
1 |
1 |
100.00 |
| V2 |
mem_cfg |
spi_device_ram_cfg |
1.620s |
25.546us |
1 |
1 |
100.00 |
| V2 |
tpm_read |
spi_device_tpm_rw |
1.850s |
38.388us |
1 |
1 |
100.00 |
| V2 |
tpm_write |
spi_device_tpm_rw |
1.850s |
38.388us |
1 |
1 |
100.00 |
| V2 |
tpm_hw_reg |
spi_device_tpm_read_hw_reg |
2.110s |
174.158us |
1 |
1 |
100.00 |
|
|
spi_device_tpm_sts_read |
1.630s |
104.451us |
1 |
1 |
100.00 |
| V2 |
tpm_fully_random_case |
spi_device_tpm_all |
20.130s |
2.992ms |
1 |
1 |
100.00 |
| V2 |
pass_cmd_filtering |
spi_device_pass_cmd_filtering |
5.260s |
364.825us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
pass_addr_translation |
spi_device_pass_addr_payload_swap |
14.840s |
9.530ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
pass_payload_translation |
spi_device_pass_addr_payload_swap |
14.840s |
9.530ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
cmd_info_slots |
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_status |
spi_device_intercept |
6.200s |
1.521ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_jedec |
spi_device_intercept |
6.200s |
1.521ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_sfdp |
spi_device_intercept |
6.200s |
1.521ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
cmd_fast_read |
spi_device_intercept |
6.200s |
1.521ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_pipeline |
spi_device_intercept |
6.200s |
1.521ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
flash_cmd_upload |
spi_device_upload |
8.840s |
2.331ms |
1 |
1 |
100.00 |
| V2 |
mailbox_command |
spi_device_mailbox |
5.310s |
218.645us |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_outside_command |
spi_device_mailbox |
5.310s |
218.645us |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_inside_command |
spi_device_mailbox |
5.310s |
218.645us |
1 |
1 |
100.00 |
| V2 |
cmd_read_buffer |
spi_device_flash_mode |
12.980s |
2.335ms |
1 |
1 |
100.00 |
|
|
spi_device_read_buffer_direct |
3.830s |
523.986us |
1 |
1 |
100.00 |
| V2 |
cmd_dummy_cycle |
spi_device_mailbox |
5.310s |
218.645us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
quad_spi |
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
dual_spi |
spi_device_flash_all |
28.950s |
10.209ms |
1 |
1 |
100.00 |
| V2 |
4b_3b_feature |
spi_device_cfg_cmd |
4.610s |
3.661ms |
1 |
1 |
100.00 |
| V2 |
write_enable_disable |
spi_device_cfg_cmd |
4.610s |
3.661ms |
1 |
1 |
100.00 |
| V2 |
TPM_with_flash_or_passthrough_mode |
spi_device_flash_and_tpm |
48.480s |
5.384ms |
1 |
1 |
100.00 |
| V2 |
tpm_and_flash_trans_with_min_inactive_time |
spi_device_flash_and_tpm_min_idle |
2.913m |
30.887ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_device_stress_all |
3.625m |
34.584ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_device_alert_test |
1.670s |
47.443us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_device_intr_test |
1.620s |
35.515us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_device_tl_errors |
3.040s |
65.618us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_device_tl_errors |
3.040s |
65.618us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_device_csr_hw_reset |
1.860s |
60.029us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.900s |
71.162us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
16.940s |
4.451ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
4.100s |
153.258us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_device_csr_hw_reset |
1.860s |
60.029us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.900s |
71.162us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
16.940s |
4.451ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
4.100s |
153.258us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
22 |
22 |
100.00 |
| V2S |
tl_intg_err |
spi_device_sec_cm |
1.880s |
36.748us |
1 |
1 |
100.00 |
|
|
spi_device_tl_intg_err |
12.420s |
5.422ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_device_tl_intg_err |
12.420s |
5.422ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_device_flash_mode_ignore_cmds |
1.700s |
19.840us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
33 |
33 |
100.00 |