SRAM_CTRL/MAIN Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.190s	1.029ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.780s	39.250us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.580s	45.502us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.420s	153.872us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.770s	112.152us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.570s	348.245us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.580s	45.502us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	112.152us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.888m	9.399ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.090m	11.402ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.312m	18.780ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.272m	2.857ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.686m	49.850ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.446m	63.692ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	25.810s	7.478ms	1	1	100.00
V2	executable	sram_ctrl_executable	16.699m	90.105ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	21.080s	1.568ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.935m	94.064ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	17.550s	1.468ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	26.970s	791.836us	1	1	100.00
		sram_ctrl_throughput_w_readback	59.570s	903.000us	1	1	100.00
V2	regwen	sram_ctrl_regwen	29.650s	1.829ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.080s	359.371us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	25.259m	92.049ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.600s	16.646us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.980s	308.773us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.980s	308.773us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.780s	39.250us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	45.502us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	112.152us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	31.690us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.780s	39.250us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	45.502us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	112.152us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	31.690us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.490s	3.926ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.520s	3.721us	0	1	0.00
		sram_ctrl_tl_intg_err	2.460s	142.818us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.520s	3.721us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.460s	142.818us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.650s	1.829ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	29.650s	1.829ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.580s	45.502us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.699m	90.105ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.699m	90.105ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.699m	90.105ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	25.810s	7.478ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.900s	1.334ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.490s	3.926ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.610s	671.177us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.190s	1.029ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.190s	1.029ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.699m	90.105ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.520s	3.721us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	25.810s	7.478ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.520s	3.721us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.520s	3.721us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.190s	1.029ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.520s	3.721us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	34.200s	5.560ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.64940243792889363842586043472311902071541522523470914754015671974458137629096
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 671177318 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2d) != exp (0x55)
        UVM_INFO @ 671177318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.38827651813853614300359701916032261947367819449822370758892793816176927295217
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3721291 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3721291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---