SYSRST_CTRL Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: `891c607`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.650s	2.111ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	3.250s	2.486ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.980s	2.405ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.790s	2.362ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	2.250s	4.249ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.830s	2.073ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	15.720s	42.099ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.210s	3.201ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	3.680s	2.068ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.830s	2.073ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.210s	3.201ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.461m	47.941ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	2.076m	60.727ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	2.110s	3.278ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.320s	3.408ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	6.010s	2.510ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	5.730s	2.119ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	2.420s	4.065ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.820s	2.649ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.280s	3.081ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	42.900s	41.335ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	16.030s	7.429ms	0	1	0.00
V2	alert_test	sysrst_ctrl_alert_test	2.060s	2.057ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.610s	2.037ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.560s	2.260ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.560s	2.260ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	2.250s	4.249ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.830s	2.073ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.210s	3.201ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	16.210s	5.251ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	2.250s	4.249ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.830s	2.073ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.210s	3.201ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	16.210s	5.251ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.306m	42.010ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	46.490s	42.668ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	46.490s	42.668ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.840s	11.528ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:

Test sysrst_ctrl_stress_all has 1 failures.

0.sysrst_ctrl_stress_all.36049083103709246058226768259252218516599474370013906638725432205685626988848
Line 382, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 6899734766 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 6962234766 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 7412255538 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 7428750476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---