UART Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: 891c607

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.890s	538.452us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.570s	21.172us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.400s	15.042us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.100s	502.665us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.910s	25.098us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.890s	18.502us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.400s	15.042us	1	1	100.00
		uart_csr_aliasing	1.910s	25.098us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	27.920s	20.107ms	1	1	100.00
V2	parity	uart_smoke	2.890s	538.452us	1	1	100.00
		uart_tx_rx	27.920s	20.107ms	1	1	100.00
V2	parity_error	uart_intr	1.400m	265.086ms	1	1	100.00
		uart_rx_parity_err	26.580s	20.992ms	1	1	100.00
V2	watermark	uart_tx_rx	27.920s	20.107ms	1	1	100.00
		uart_intr	1.400m	265.086ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.732m	81.491ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	3.496m	103.961ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	35.350s	95.174ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.400m	265.086ms	1	1	100.00
V2	rx_break_err	uart_intr	1.400m	265.086ms	1	1	100.00
V2	rx_timeout	uart_intr	1.400m	265.086ms	1	1	100.00
V2	perf	uart_perf	3.882m	11.572ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.660s	2.936ms	1	1	100.00
V2	line_loopback	uart_loopback	5.660s	2.936ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	22.660s	16.878ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.810s	38.384ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.690s	904.952us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.370s	3.806ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	40.070s	41.758ms	1	1	100.00
V2	stress_all	uart_stress_all	2.826m	289.550ms	1	1	100.00
V2	alert_test	uart_alert_test	1.930s	15.919us	1	1	100.00
V2	intr_test	uart_intr_test	1.510s	12.857us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.970s	25.438us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.970s	25.438us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.570s	21.172us	1	1	100.00
		uart_csr_rw	1.400s	15.042us	1	1	100.00
		uart_csr_aliasing	1.910s	25.098us	1	1	100.00
		uart_same_csr_outstanding	1.650s	24.861us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.570s	21.172us	1	1	100.00
		uart_csr_rw	1.400s	15.042us	1	1	100.00
		uart_csr_aliasing	1.910s	25.098us	1	1	100.00
		uart_same_csr_outstanding	1.650s	24.861us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.880s	226.354us	1	1	100.00
		uart_tl_intg_err	2.020s	231.698us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.020s	231.698us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.098m	17.761ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00