CHIP Simulation Results

Tuesday June 03 2025 20:24:31 UTC

GitHub Revision: `891c607`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.978m	3.139ms	1	1	100.00
		chip_sw_example_rom	1.225m	2.709ms	1	1	100.00
		chip_sw_example_manufacturer	1.533m	3.016ms	1	1	100.00
		chip_sw_example_concurrency	2.213m	3.169ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.318m	4.465ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.379m	6.617ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.540m	5.139ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	50.432m	29.036ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	9.750m	11.490ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	50.432m	29.036ms	1	1	100.00
		chip_csr_rw	5.379m	6.617ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.030s	205.119us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.488m	4.009ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.488m	4.009ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.488m	4.009ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.600m	4.248ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.600m	4.248ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.707m	4.176ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.745m	4.479ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.731m	4.024ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	13.944m	8.133ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.579m	9.074ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.443m	8.947ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	1.966m	3.922ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.966m	3.922ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.535m	3.748ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.188m	5.203ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.711m	3.837ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.210m	3.403ms	1	1	100.00
		chip_tap_straps_testunlock0	3.809m	4.563ms	1	1	100.00
		chip_tap_straps_rma	4.282m	4.455ms	1	1	100.00
		chip_tap_straps_prod	9.107m	10.178ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.013m	3.038ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.068m	8.133ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.578m	6.292ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.578m	6.292ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.404m	7.097ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	43.310m	25.519ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.580m	4.356ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.617m	5.741ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.720m	18.679ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.221m	3.552ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.215m	6.426ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.617m	3.417ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.361m	10.184ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.427m	2.502ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.503m	4.468ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.521m	2.989ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.904m	2.877ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.089m	6.865ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.500m	5.439ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.250m	3.327ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.500m	5.439ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.725m	3.478ms	1	1	100.00
		chip_sw_aes_smoketest	2.967m	3.055ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.422m	2.697ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.945m	2.374ms	1	1	100.00
		chip_sw_csrng_smoketest	2.971m	3.041ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.048m	3.874ms	1	1	100.00
		chip_sw_gpio_smoketest	2.600m	3.150ms	1	1	100.00
		chip_sw_hmac_smoketest	3.371m	3.166ms	1	1	100.00
		chip_sw_kmac_smoketest	2.409m	2.986ms	1	1	100.00
		chip_sw_otbn_smoketest	20.179m	10.693ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.827m	5.259ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.613m	6.052ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.597m	3.097ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.672m	2.526ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.975m	3.104ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.770m	1.921ms	1	1	100.00
		chip_sw_uart_smoketest	2.137m	3.019ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.179m	2.649ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.126m	4.325ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.084h	60.910ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.066m	14.822ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.432m	6.118ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.195m	2.814ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.702m	3.420ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.752h	54.661ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.894h	57.686ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	46.810s	2.805ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	46.810s	2.805ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	50.432m	29.036ms	1	1	100.00
		chip_same_csr_outstanding	16.056m	14.154ms	1	1	100.00
		chip_csr_hw_reset	2.318m	4.465ms	1	1	100.00
		chip_csr_rw	5.379m	6.617ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	50.432m	29.036ms	1	1	100.00
		chip_same_csr_outstanding	16.056m	14.154ms	1	1	100.00
		chip_csr_hw_reset	2.318m	4.465ms	1	1	100.00
		chip_csr_rw	5.379m	6.617ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	42.590s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.880s	50.694us	1	1	100.00
		xbar_smoke_large_delays	55.530s	9.549ms	1	1	100.00
		xbar_smoke_slow_rsp	33.770s	4.020ms	1	1	100.00
		xbar_random_zero_delays	33.260s	621.519us	1	1	100.00
		xbar_random_large_delays	2.148m	22.382ms	1	1	100.00
		xbar_random_slow_rsp	1.603m	11.045ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	20.730s	799.068us	1	1	100.00
		xbar_error_and_unmapped_addr	8.800s	180.845us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	5.920s	147.243us	1	1	100.00
		xbar_error_and_unmapped_addr	8.800s	180.845us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	17.610s	573.292us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.524m	54.278ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	19.640s	367.401us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	7.140s	86.737us	1	1	100.00
		xbar_stress_all_with_error	36.380s	1.945ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.193m	272.447us	1	1	100.00
		xbar_stress_all_with_reset_error	2.686m	6.274ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.066m	14.822ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	35.514m	29.178ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.187m	15.386ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.549m	10.627ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.161m	15.198ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.965m	15.631ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.624m	15.601ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.244m	15.258ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.420s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.830s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.450s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.190s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	32.330s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28.110s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.940s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.390s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.140s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.120s	10.140us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.620s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.670s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.270s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	28.630s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.570s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.640s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.430s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.310s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.510s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.900s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.480s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	30.020s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.390s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.680s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.150s	10.360us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.070m	10.777ms	1	1	100.00
		rom_e2e_asm_init_dev	39.492m	15.889ms	1	1	100.00
		rom_e2e_asm_init_prod	39.271m	15.316ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.614m	15.556ms	1	1	100.00
		rom_e2e_asm_init_rma	35.748m	14.678ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.299m	15.161ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.649m	14.777ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.254m	15.098ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.973m	16.065ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.871m	34.987ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.871m	34.987ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.655m	3.367ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.221m	3.552ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.161m	2.183ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.771m	2.757ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.025m	9.432ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.575m	3.123ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.079m	5.588ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.645m	4.916ms	1	1	100.00
		chip_plic_all_irqs_10	3.973m	3.543ms	1	1	100.00
		chip_plic_all_irqs_20	6.291m	3.871ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.271m	3.689ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.157m	9.798ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.618m	4.388ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.881m	2.858ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.018m	11.427ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.997m	8.353ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.143m	6.167ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.697m	7.380ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.208h	254.536ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.398m	3.571ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.827m	5.259ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.398m	3.571ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.697m	7.235ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.697m	7.235ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.601m	7.569ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.078m	4.086ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.384m	6.485ms	1	1	100.00
		chip_sw_aes_idle	2.771m	2.757ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.490m	2.275ms	1	1	100.00
		chip_sw_kmac_idle	2.167m	2.631ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.203m	4.481ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.190m	4.694ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.893m	4.313ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.308m	4.066ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.605m	11.018ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.070m	3.473ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.173m	4.929ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.458m	4.599ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.697m	4.665ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.528m	3.779ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.332m	4.456ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.404m	7.097ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.484m	4.735ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.458m	4.599ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.697m	4.665ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.580m	4.356ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.617m	5.741ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.720m	18.679ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.221m	3.552ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.215m	6.426ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.617m	3.417ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.361m	10.184ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.427m	2.502ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.503m	4.468ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.521m	2.989ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.681m	2.731ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.364m	4.695ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.040m	7.268ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.102m	23.974ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.435m	2.516ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.380m	2.936ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.069m	7.279ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.559m	3.119ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.840m	4.919ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.344m	23.291ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.273h	51.464ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.404m	7.097ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.431m	4.467ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.740m	3.177ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.997m	8.353ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.544m	6.072ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.999m	2.714ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.122m	6.266ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.551m	2.918ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	56.674m	21.421ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.753m	3.227ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.174m	6.617ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.753m	3.227ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.544m	6.072ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.488m	3.312ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.876m	16.595ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.886m	5.395ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.617m	5.741ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.780m	3.647ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.580m	4.356ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.615m	45.004ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.876m	16.595ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.196m	4.003ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.268m	11.367ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.306m	5.545ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.615m	45.004ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.306m	5.545ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.306m	5.545ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.306m	5.545ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.306m	5.545ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.135m	7.779ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.771m	5.574ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.385m	4.993ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.385m	4.993ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.089m	3.179ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.617m	3.417ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.490m	2.275ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.551m	3.363ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.819m	3.725ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.885m	5.362ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.923m	5.070ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.951m	5.115ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.024m	4.639ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.268m	11.367ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.361m	10.184ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	25.171m	13.184ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.025m	9.432ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.055m	14.375ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.434m	2.689ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.403m	3.743ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.427m	2.502ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.268m	11.367ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.213m	2.993ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	24.896m	11.987ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.167m	2.631ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.079m	5.588ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.210m	3.403ms	1	1	100.00
		chip_tap_straps_rma	4.282m	4.455ms	1	1	100.00
		chip_tap_straps_prod	9.107m	10.178ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.964m	2.678ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	19.099m	10.399ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.306m	5.545ms	1	1	100.00
		chip_sw_flash_rma_unlocked	59.615m	45.004ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.391m	3.155ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.638m	6.527ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.251m	7.438ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.464m	7.227ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.268m	11.367ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.440m	8.617ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.777m	9.898ms	1	1	100.00
		chip_prim_tl_access	2.135m	7.779ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.484m	4.735ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.070m	3.473ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.173m	4.929ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.458m	4.599ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.697m	4.665ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.528m	3.779ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.332m	4.456ms	1	1	100.00
		chip_tap_straps_dev	2.210m	3.403ms	1	1	100.00
		chip_tap_straps_rma	4.282m	4.455ms	1	1	100.00
		chip_tap_straps_prod	9.107m	10.178ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.683m	8.219ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.843m	3.022ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.390m	3.073ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.391m	3.222ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.498m	3.403ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.156m	29.615ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.683m	8.219ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.053h	52.248ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.016h	49.491ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.882m	8.227ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	56.303m	48.428ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.156m	29.615ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.246m	2.439ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.202m	2.663ms	1	1	100.00
		rom_volatile_raw_unlock	1.181m	2.631ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.555m	16.687ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.720m	18.679ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.384m	6.485ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.384m	6.485ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.384m	6.485ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.427m	3.909ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.876m	16.595ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.427m	3.909ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.268m	11.367ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	7.070m	4.209ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.576m	3.121ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.876m	16.595ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.427m	3.909ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.268m	11.367ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	7.070m	4.209ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.576m	3.121ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.563m	5.470ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.964m	2.678ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.391m	3.155ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.638m	6.527ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.251m	7.438ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.464m	7.227ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.792m	4.764ms	1	1	100.00
		chip_prim_tl_access	2.135m	7.779ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.135m	7.779ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.719m	9.592ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.583m	6.573ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.092m	26.301ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.334m	7.701ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.476m	6.768ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.698m	6.315ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.824m	24.204ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	16.235m	13.555ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.697m	7.235ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.077m	12.627ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.510m	4.234ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.583m	6.573ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.045m	4.487ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	36.194m	44.012ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.869m	6.274ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.835m	5.119ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.657m	18.630ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.783m	6.152ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	18.702m	14.228ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	28.436m	31.457ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.119m	3.201ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.440m	8.617ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.440m	8.617ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	18.702m	14.228ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.657m	18.630ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.510m	4.234ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.827m	5.259ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.382m	4.638ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.163m	4.886ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.703m	4.765ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.157m	9.798ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.046m	2.654ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	11.143m	6.167ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.850m	4.608ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.005m	4.998ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.740m	2.866ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.576m	3.121ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.163m	4.886ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.163m	4.886ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	19.527m	16.539ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.629m	13.433ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.382m	4.638ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.917m	4.059ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.795m	6.459ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.282m	4.455ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.683m	8.219ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.645m	4.916ms	1	1	100.00
		chip_plic_all_irqs_10	3.973m	3.543ms	1	1	100.00
		chip_plic_all_irqs_20	6.291m	3.871ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.403m	3.233ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.050m	3.339ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.066m	14.822ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.849m	7.455ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.716m	2.397ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.789m	2.646ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.894m	3.062ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.070m	4.209ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.503m	4.468ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.572m	6.740ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.291m	8.646ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.777m	9.898ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.578m	6.292ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.783m	6.152ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.562m	22.492ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.655m	2.674ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.509m	3.806ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.982m	4.363ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.562m	22.492ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.562m	22.492ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	35.053m	20.027ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	35.053m	20.027ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.661m	5.810ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.871m	34.987ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.908m	2.822ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.093m	3.184ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.328m	4.075ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.527m	3.732ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.101m	8.823ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.279h	31.361ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.218m	13.021ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.998m	3.044ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.611m	3.040ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.640m	2.565ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.480h	71.731ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.221m	3.580ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.335m	12.301ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.184m	11.823ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.902m	11.282ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.317m	3.957ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.298m	4.291ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.868m	3.752ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.390s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.913m	5.743ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.271m	2.857ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.588m	4.800ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.119m	6.478ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.938m	2.875ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.767m	5.220ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.711m	2.732ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.326m	4.742ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.495m	5.782ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.575m	4.463ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	18.702m	14.228ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.335m	12.301ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.184m	11.823ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.902m	11.282ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.034m	5.932ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.570m	5.307ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.496h	38.227ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.496h	38.227ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.059m	3.829ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.600m	4.248ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.751m	19.095ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.686m	3.169ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.209m	4.918ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.990m	2.003ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.761m	2.831ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.101m	3.546ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	14.997s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.882m	3.798ms	1	1	100.00
		TOTAL			284	325	87.38

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.84660373191680920817684292385911815777371752957814487754366704521180526310900
    Line 631, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.48553266621004204220485060523754685403823398410094310731661386246686235791167
    Line 693, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.14998415528363242683646809123175343140631369726695367242912152984856502364853
    Line 651, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.38524094439170305994025241943140120024794712733110213229582769929649949164486
    Line 745, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.67182214410610703676827935193511776160526484913844520052448053566588481332671
    Line 692, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.87506353365003893356372183483429373936686880716868568706651207766209484261054
    Line 565, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.107697922640502138085807660005867102153764112297346105219827368346884594872064
    Line 575, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.33543250017262460396684119527072578969346539602854023389124593765536354177164
    Line 586, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.84054166501087989298731296076414098712920381783627927418375770851181306470433
    Line 596, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.11287470694906473522443629073118863245320240538932570270263229502809684273762
    Line 600, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.110655170113570299839184589920580112121718625391055586634725692823703445149093
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.38328580173087241354151594276874353041223829658435065481252312307732629092922
    Line 639, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.63572629633594709516361463573130102006484388554800297365715762862344476532533
    Line 651, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.49400351049172930830601357529240682960943284140294462098987023776849295529658
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.987s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.94149413135482923006466096591378449374361224888243855391783571517232824086112
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.379s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3639077739058022473365385088280528871252119258762239941481535200361938467120
    Line 792, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.16071454239592686602864015614400845252568866882327251357629765947664253121918
    Line 749, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.37934065648436797520095140990422798569306249391911356948848569078391650669900
    Line 771, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.57170168291029966441986139534588065421440009389453560825524421756395692271704
    Line 728, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.9004872251155276660614770778441648362236618121791893882551322705457103842768
    Line 668, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3747.872500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3747.872500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.38272449599776657320328110357977465320561827069422981682940474176700657847467
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2397.026312 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2397.026312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@104907) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.5854882530399449856091860391612826336217081389027985743409772921766682347557
Line 455, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4886.211600 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@104907) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4886.211600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.83755752200332686588191733699509898705451800868078911204229195022816292211950
    Line 448, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34986.875987 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34986.875987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.89705503370056579160764793241683728524152021262338152726620496584026444410344
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3123.108072 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3123.108072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.79477002799605778984292110453592416244998249721171135862657751338599584060893
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2857.572440 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2857.572440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.17928216761204202603968811692286306595664566502744866801914628935599567059457
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2713.983954 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2713.983954 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33799) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.54873200562540843582589604768651148407330584505976356119107714422604502074645
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2804.701584 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33799) { a_addr: 'h106f8  a_data: 'h3834114e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h1ae79  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2804.701584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.21861406272966331458136451783277642917755575055628952313479337512292469036367
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3545.924758 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3545.924758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.115411024313562928423350605967029025613103281134467597313151722487822050633469
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2564.821280 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2564.821280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.92485035971642270719574401592075784362655496294314733715552130802892265479037
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2814.118500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2814.118500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.37780599915507839026805312014585770572351133418478743227092088958064590806782
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3420.119500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3420.119500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.44689400728055889646865357678567724145829506068216015658806328189105323762142
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 25519.286406 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 25519.286406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.94108250441657612277911960080867139039559833877887981306252140596885229279197
    Line 497, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3579.672152 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3579.672152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.79245317188742308173253197788069951165198344129105385098871785835123870368203
    Line 633, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1941949042784819315416633682045952052238903433296210047433362403605616810283
    Line 778, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```