ADC_CTRL Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.110s	6.027ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.220s	1.161ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.590s	558.008us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	19.870s	26.439ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.130s	1.312ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	600.800us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.590s	558.008us	1	1	100.00
		adc_ctrl_csr_aliasing	3.130s	1.312ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.681m	168.377ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.486m	328.512ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.422m	164.827ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	14.196m	500.109ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	9.892m	355.654ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	4.121m	201.537ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.411m	158.031ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	8.612m	367.439ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	5.240s	4.125ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	24.330s	28.650ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	25.480s	63.693ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	6.242m	414.902ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.830s	514.632us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.980s	471.527us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.020s	755.919us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.020s	755.919us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.220s	1.161ms	1	1	100.00
		adc_ctrl_csr_rw	2.590s	558.008us	1	1	100.00
		adc_ctrl_csr_aliasing	3.130s	1.312ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.870s	4.232ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.220s	1.161ms	1	1	100.00
		adc_ctrl_csr_rw	2.590s	558.008us	1	1	100.00
		adc_ctrl_csr_aliasing	3.130s	1.312ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.870s	4.232ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	7.100s	8.384ms	1	1	100.00
		adc_ctrl_tl_intg_err	18.190s	8.134ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	18.190s	8.134ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.430s	6.969ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00