CSRNG Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	43.577us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	70.681us	1	1	100.00
V1	csr_rw	csrng_csr_rw	4.000s	38.293us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	17.000s	988.572us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	142.815us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	33.910us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	38.293us	1	1	100.00
		csrng_csr_aliasing	7.000s	142.815us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	6.000s	146.897us	0	1	0.00
V2	alerts	csrng_alert	14.000s	477.682us	1	1	100.00
V2	err	csrng_err	4.000s	1.939us	0	1	0.00
V2	cmds	csrng_cmds	1.267m	4.045ms	1	1	100.00
V2	life cycle	csrng_cmds	1.267m	4.045ms	1	1	100.00
V2	stress_all	csrng_stress_all	4.717m	7.302ms	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	158.912us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	39.475us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	8.000s	295.313us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	8.000s	295.313us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	70.681us	1	1	100.00
		csrng_csr_rw	4.000s	38.293us	1	1	100.00
		csrng_csr_aliasing	7.000s	142.815us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	30.658us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	70.681us	1	1	100.00
		csrng_csr_rw	4.000s	38.293us	1	1	100.00
		csrng_csr_aliasing	7.000s	142.815us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	30.658us	1	1	100.00
V2		TOTAL			7	9	77.78
V2S	tl_intg_err	csrng_sec_cm	8.000s	264.880us	1	1	100.00
		csrng_tl_intg_err	8.000s	210.722us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	21.656us	1	1	100.00
		csrng_csr_rw	4.000s	38.293us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	14.000s	477.682us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	4.717m	7.302ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	14.000s	477.682us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	4.717m	7.302ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	14.000s	477.682us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	8.000s	210.722us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
		csrng_sec_cm	8.000s	264.880us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	146.897us	0	1	0.00
		csrng_err	4.000s	1.939us	0	1	0.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	15.000s	1.026ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			16	19	84.21

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed has 1 failures:

  • Test csrng_intr has 1 failures.

    • 0.csrng_intr.67650493842514310270977810114907081603936748848000099957018711417970246247259
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 146896877 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
        UVM_ERROR @ 146896877 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
        UVM_INFO @ 146896877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 1 failures:

  • Test csrng_err has 1 failures.

    • 0.csrng_err.87269002063744048726200634826890349920504413679073762411122631012518489462459
      Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 1938600 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
        UVM_ERROR @   1938600 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
        UVM_INFO @   1938600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.69520604559282180715095714182979969675296407988680579888083154270334936058925
      Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1025500172 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1025500172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---