EDN Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.780s	18.055us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.710s	137.994us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.650s	43.861us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.210s	1.517ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.210s	48.341us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.850s	86.182us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.650s	43.861us	1	1	100.00
		edn_csr_aliasing	2.210s	48.341us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.500s	88.756us	1	1	100.00
V2	csrng_commands	edn_genbits	2.500s	88.756us	1	1	100.00
V2	genbits	edn_genbits	2.500s	88.756us	1	1	100.00
V2	interrupts	edn_intr	1.620s	32.016us	1	1	100.00
V2	alerts	edn_alert	1.980s	27.557us	1	1	100.00
V2	errs	edn_err	1.900s	42.637us	1	1	100.00
V2	disable	edn_disable	1.750s	14.157us	1	1	100.00
		edn_disable_auto_req_mode	1.870s	32.972us	1	1	100.00
V2	stress_all	edn_stress_all	3.700s	158.671us	1	1	100.00
V2	intr_test	edn_intr_test	1.680s	29.786us	1	1	100.00
V2	alert_test	edn_alert_test	1.820s	51.514us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.420s	380.251us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.420s	380.251us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.710s	137.994us	1	1	100.00
		edn_csr_rw	1.650s	43.861us	1	1	100.00
		edn_csr_aliasing	2.210s	48.341us	1	1	100.00
		edn_same_csr_outstanding	2.210s	138.437us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.710s	137.994us	1	1	100.00
		edn_csr_rw	1.650s	43.861us	1	1	100.00
		edn_csr_aliasing	2.210s	48.341us	1	1	100.00
		edn_same_csr_outstanding	2.210s	138.437us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.970s	531.921us	1	1	100.00
		edn_tl_intg_err	2.210s	272.789us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.830s	19.493us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.980s	27.557us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.970s	531.921us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.970s	531.921us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.970s	531.921us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.970s	531.921us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.980s	27.557us	1	1	100.00
		edn_sec_cm	4.970s	531.921us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.980s	27.557us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.210s	272.789us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	27.610s	1.491ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00