HMAC Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.490s 109.728us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.830s 36.141us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.730s 18.067us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.900s 724.795us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.940s 300.304us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.040s 128.358us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.730s 18.067us 1 1 100.00
hmac_csr_aliasing 4.940s 300.304us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 28.270s 12.229ms 1 1 100.00
V2 back_pressure hmac_back_pressure 12.330s 1.579ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.950s 617.621us 1 1 100.00
hmac_test_sha384_vectors 20.350s 3.318ms 1 1 100.00
hmac_test_sha512_vectors 6.920m 56.049ms 1 1 100.00
hmac_test_hmac256_vectors 7.620s 303.127us 1 1 100.00
hmac_test_hmac384_vectors 7.380s 779.534us 1 1 100.00
hmac_test_hmac512_vectors 11.520s 377.752us 1 1 100.00
V2 burst_wr hmac_burst_wr 7.440s 3.161ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.953m 4.932ms 1 1 100.00
V2 error hmac_error 13.130s 2.770ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.078m 1.832ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.490s 109.728us 1 1 100.00
hmac_long_msg 28.270s 12.229ms 1 1 100.00
hmac_back_pressure 12.330s 1.579ms 1 1 100.00
hmac_datapath_stress 8.953m 4.932ms 1 1 100.00
hmac_burst_wr 7.440s 3.161ms 1 1 100.00
hmac_stress_all 19.519m 235.389ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.490s 109.728us 1 1 100.00
hmac_long_msg 28.270s 12.229ms 1 1 100.00
hmac_back_pressure 12.330s 1.579ms 1 1 100.00
hmac_datapath_stress 8.953m 4.932ms 1 1 100.00
hmac_wipe_secret 1.078m 1.832ms 1 1 100.00
hmac_test_sha256_vectors 7.950s 617.621us 1 1 100.00
hmac_test_sha384_vectors 20.350s 3.318ms 1 1 100.00
hmac_test_sha512_vectors 6.920m 56.049ms 1 1 100.00
hmac_test_hmac256_vectors 7.620s 303.127us 1 1 100.00
hmac_test_hmac384_vectors 7.380s 779.534us 1 1 100.00
hmac_test_hmac512_vectors 11.520s 377.752us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.490s 109.728us 1 1 100.00
hmac_long_msg 28.270s 12.229ms 1 1 100.00
hmac_back_pressure 12.330s 1.579ms 1 1 100.00
hmac_datapath_stress 8.953m 4.932ms 1 1 100.00
hmac_burst_wr 7.440s 3.161ms 1 1 100.00
hmac_error 13.130s 2.770ms 1 1 100.00
hmac_wipe_secret 1.078m 1.832ms 1 1 100.00
hmac_test_sha256_vectors 7.950s 617.621us 1 1 100.00
hmac_test_sha384_vectors 20.350s 3.318ms 1 1 100.00
hmac_test_sha512_vectors 6.920m 56.049ms 1 1 100.00
hmac_test_hmac256_vectors 7.620s 303.127us 1 1 100.00
hmac_test_hmac384_vectors 7.380s 779.534us 1 1 100.00
hmac_test_hmac512_vectors 11.520s 377.752us 1 1 100.00
hmac_stress_all 19.519m 235.389ms 1 1 100.00
V2 stress_all hmac_stress_all 19.519m 235.389ms 1 1 100.00
V2 alert_test hmac_alert_test 1.570s 11.365us 1 1 100.00
V2 intr_test hmac_intr_test 1.620s 14.778us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.110s 165.823us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.110s 165.823us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.830s 36.141us 1 1 100.00
hmac_csr_rw 1.730s 18.067us 1 1 100.00
hmac_csr_aliasing 4.940s 300.304us 1 1 100.00
hmac_same_csr_outstanding 1.860s 21.709us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.830s 36.141us 1 1 100.00
hmac_csr_rw 1.730s 18.067us 1 1 100.00
hmac_csr_aliasing 4.940s 300.304us 1 1 100.00
hmac_same_csr_outstanding 1.860s 21.709us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.100s 346.691us 1 1 100.00
hmac_tl_intg_err 3.130s 99.217us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.130s 99.217us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.490s 109.728us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.970s 253.133us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.924m 9.949ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.060s 57.483us 1 1 100.00
TOTAL 28 28 100.00