I2C Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: `2e10a15`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.830s	7.233ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.360s	1.741ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.630s	19.247us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.620s	18.682us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.390s	1.465ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.910s	100.367us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.710s	147.854us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.620s	18.682us	1	1	100.00
		i2c_csr_aliasing	1.910s	100.367us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.440s	200.311us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.684m	6.281ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.318m	8.796ms	1	1	100.00
V2	host_override	i2c_host_override	1.540s	21.403us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.889m	16.824ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	56.360s	1.463ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.700s	440.795us	1	1	100.00
		i2c_host_fifo_fmt_empty	23.740s	664.916us	1	1	100.00
		i2c_host_fifo_reset_rx	6.440s	602.356us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	28.750s	16.374ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.420s	1.188ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.520s	566.822us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.950s	2.154ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.418m	26.544ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.820s	1.445ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.430s	691.218us	1	1	100.00
		i2c_target_intr_smoke	6.040s	3.104ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.810s	266.341us	1	1	100.00
		i2c_target_fifo_reset_tx	1.820s	167.212us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.940s	20.531ms	1	1	100.00
		i2c_target_stress_rd	11.430s	691.218us	1	1	100.00
		i2c_target_intr_stress_wr	2.970s	6.440ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.830s	18.540ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.601m	3.181ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.060s	1.283ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.280s	298.483us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.400s	752.210us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.000s	645.837us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.318m	8.796ms	1	1	100.00
		i2c_host_perf_precise	4.046m	24.556ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.420s	1.188ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.930s	505.041us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.850s	521.674us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.420s	431.053us	1	1	100.00
		i2c_target_nack_txstretch	1.840s	148.702us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.890s	560.675us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.520s	505.035us	1	1	100.00
V2	alert_test	i2c_alert_test	1.500s	143.886us	1	1	100.00
V2	intr_test	i2c_intr_test	1.470s	31.524us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.980s	206.247us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.980s	206.247us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.630s	19.247us	1	1	100.00
		i2c_csr_rw	1.620s	18.682us	1	1	100.00
		i2c_csr_aliasing	1.910s	100.367us	1	1	100.00
		i2c_same_csr_outstanding	2.760s	808.224us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.630s	19.247us	1	1	100.00
		i2c_csr_rw	1.620s	18.682us	1	1	100.00
		i2c_csr_aliasing	1.910s	100.367us	1	1	100.00
		i2c_same_csr_outstanding	2.760s	808.224us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.710s	131.755us	1	1	100.00
		i2c_sec_cm	1.780s	78.316us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.710s	131.755us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	35.000s	1.102ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.710s	102.733us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	16.290s	6.843ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.47996023358766602748953623790388759282838497413904663542313079560600777299557
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1102439024 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1102439024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.63607797298594814236278383080228133169524274139788542654053814088516572375738
    Line 133, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6843274932 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6843274932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.73955168738479098999786963696364284530588689628018447740179675080115119587174
Line 125, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 6281219110 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1807000

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.57789707267044375458791262975011986435116192394493274233526002997322701130188
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 102733111 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 102733111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.61411012685671748223793055277886475641518760932077512525283125215444704526095
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @ 566822266 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```