KEYMGR Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.340s	406.820us	1	1	100.00
V1	random	keymgr_random	3.210s	81.338us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.160s	65.338us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.380s	18.895us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.490s	2.369ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	4.620s	69.082us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.370s	86.678us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.380s	18.895us	1	1	100.00
		keymgr_csr_aliasing	4.620s	69.082us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	12.250s	1.181ms	1	1	100.00
V2	sideload	keymgr_sideload	7.810s	612.867us	1	1	100.00
		keymgr_sideload_kmac	3.920s	893.015us	1	1	100.00
		keymgr_sideload_aes	22.220s	3.142ms	1	1	100.00
		keymgr_sideload_otbn	3.400s	127.229us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.530s	77.948us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.190s	151.576us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.100s	93.113us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.000s	179.727us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.520s	211.654us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.960s	53.843us	1	1	100.00
V2	stress_all	keymgr_stress_all	8.450s	259.416us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.700s	11.111us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.690s	100.062us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.470s	176.959us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.470s	176.959us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.160s	65.338us	1	1	100.00
		keymgr_csr_rw	2.380s	18.895us	1	1	100.00
		keymgr_csr_aliasing	4.620s	69.082us	1	1	100.00
		keymgr_same_csr_outstanding	4.010s	483.769us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.160s	65.338us	1	1	100.00
		keymgr_csr_rw	2.380s	18.895us	1	1	100.00
		keymgr_csr_aliasing	4.620s	69.082us	1	1	100.00
		keymgr_same_csr_outstanding	4.010s	483.769us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
		keymgr_tl_intg_err	2.340s	19.484us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.350s	65.876us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.350s	65.876us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.350s	65.876us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.350s	65.876us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.110s	169.699us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.340s	19.484us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.350s	65.876us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	12.250s	1.181ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.210s	81.338us	1	1	100.00
		keymgr_csr_rw	2.380s	18.895us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.210s	81.338us	1	1	100.00
		keymgr_csr_rw	2.380s	18.895us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.210s	81.338us	1	1	100.00
		keymgr_csr_rw	2.380s	18.895us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.190s	151.576us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.520s	211.654us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.520s	211.654us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.210s	81.338us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.710s	206.147us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.900s	115.408us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.190s	151.576us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.900s	115.408us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.900s	115.408us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.900s	115.408us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.730s	445.773us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.900s	115.408us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.130s	656.624us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.27610093348899334083688438725228966022925475419348892289299569918781701398305
      Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @  19483867 ps: (keymgr_csr_assert_fpv.sv:472) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @  19483867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.44092024660015808830098339644585751219915504594524078161464349038631650577762
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @ 2368527274 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @ 2368527274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---