KMAC/MASKED Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	54.690s	7.100ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.750s	62.063us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.010s	47.433us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.700s	990.962us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.970s	135.659us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.360s	345.612us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.010s	47.433us	1	1	100.00
		kmac_csr_aliasing	5.970s	135.659us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.790s	36.631us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.000s	98.865us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.700m	47.853ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.959m	9.180ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.157m	1.179s	1	1	100.00
		kmac_test_vectors_sha3_256	34.420s	3.447ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.900s	3.852ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.696m	19.078ms	1	1	100.00
		kmac_test_vectors_shake_128	3.362m	64.822ms	1	1	100.00
		kmac_test_vectors_shake_256	28.540m	241.509ms	1	1	100.00
		kmac_test_vectors_kmac	4.150s	244.938us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.970s	266.832us	1	1	100.00
V2	sideload	kmac_sideload	4.617m	27.418ms	1	1	100.00
V2	app	kmac_app	29.550s	3.817ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.912m	7.229ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.120m	27.279ms	1	1	100.00
V2	error	kmac_error	2.567m	6.119ms	1	1	100.00
V2	key_error	kmac_key_error	5.120s	2.325ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.710s	100.313us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.610s	74.917us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.730s	18.877us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	31.300s	3.856ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.820s	48.400us	1	1	100.00
V2	stress_all	kmac_stress_all	10.660m	21.349ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.540s	13.667us	1	1	100.00
V2	alert_test	kmac_alert_test	1.610s	21.258us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.430s	67.194us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.430s	67.194us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.750s	62.063us	1	1	100.00
		kmac_csr_rw	2.010s	47.433us	1	1	100.00
		kmac_csr_aliasing	5.970s	135.659us	1	1	100.00
		kmac_same_csr_outstanding	2.130s	25.356us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.750s	62.063us	1	1	100.00
		kmac_csr_rw	2.010s	47.433us	1	1	100.00
		kmac_csr_aliasing	5.970s	135.659us	1	1	100.00
		kmac_same_csr_outstanding	2.130s	25.356us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.500s	48.420us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.500s	48.420us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.500s	48.420us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.500s	48.420us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.980s	23.426us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.420s	2.607ms	1	1	100.00
		kmac_tl_intg_err	3.870s	1.060ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.870s	1.060ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.820s	48.400us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	54.690s	7.100ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.617m	27.418ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.500s	48.420us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.420s	2.607ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.420s	2.607ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.420s	2.607ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	54.690s	7.100ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.820s	48.400us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.420s	2.607ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.051m	181.500ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	54.690s	7.100ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.347m	12.766ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.72667492221045284464951382743872402354867572148534359811882278834862642306637
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  23425690 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  23425690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---