KMAC/UNMASKED Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	19.610s	1.646ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	76.576us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.850s	16.913us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.860s	508.982us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.080s	401.321us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.180s	54.628us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	16.913us	1	1	100.00
		kmac_csr_aliasing	7.080s	401.321us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.880s	24.520us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.910s	63.564us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	3.533m	3.576ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.342m	12.365ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.187m	345.375ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.611m	503.359ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.970s	6.639ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.694m	103.383ms	1	1	100.00
		kmac_test_vectors_shake_128	26.634m	164.467ms	1	1	100.00
		kmac_test_vectors_shake_256	1.468m	14.659ms	1	1	100.00
		kmac_test_vectors_kmac	2.610s	107.863us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.180s	94.039us	1	1	100.00
V2	sideload	kmac_sideload	1.202m	1.461ms	1	1	100.00
V2	app	kmac_app	2.661m	19.441ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	10.380s	3.802ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	28.410s	2.322ms	1	1	100.00
V2	error	kmac_error	2.194m	29.288ms	1	1	100.00
V2	key_error	kmac_key_error	2.960s	191.043us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	21.020s	10.222ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.420s	410.387us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.530s	953.220us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	23.670s	14.356ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.320s	40.174us	1	1	100.00
V2	stress_all	kmac_stress_all	10.917m	167.605ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.590s	15.828us	1	1	100.00
V2	alert_test	kmac_alert_test	1.710s	17.376us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.170s	489.150us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.170s	489.150us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	76.576us	1	1	100.00
		kmac_csr_rw	1.850s	16.913us	1	1	100.00
		kmac_csr_aliasing	7.080s	401.321us	1	1	100.00
		kmac_same_csr_outstanding	2.160s	100.989us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	76.576us	1	1	100.00
		kmac_csr_rw	1.850s	16.913us	1	1	100.00
		kmac_csr_aliasing	7.080s	401.321us	1	1	100.00
		kmac_same_csr_outstanding	2.160s	100.989us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.180s	315.799us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.180s	315.799us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.180s	315.799us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.180s	315.799us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.230s	781.336us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	32.010s	6.128ms	1	1	100.00
		kmac_tl_intg_err	1.570s	54.129us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.570s	54.129us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.320s	40.174us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	19.610s	1.646ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.202m	1.461ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.180s	315.799us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	32.010s	6.128ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	32.010s	6.128ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	32.010s	6.128ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	19.610s	1.646ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.320s	40.174us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	32.010s	6.128ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.471m	17.407ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	19.610s	1.646ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	14.990s	2.642ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.64787643997448069461392107722376964181374740772262823521925870633471679645266
      Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10222192353 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa0ef5000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10222192353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.107734559376353082108256696337466591056028821983590830801224132729453004914765
      Line 125, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2642277881 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2642277881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.107653452929242787764529826904560389511892538985868575018253760981170107619931
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @  54128720 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @  54128720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---