PATTGEN Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	83.515us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	5.000s	15.661us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	67.081us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	35.748us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	76.475us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	159.795us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	67.081us	1	1	100.00
		pattgen_csr_aliasing	4.000s	76.475us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.133m	34.503ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	17.000s	5.283ms	1	1	100.00
V2	error	pattgen_error	4.000s	46.482us	1	1	100.00
V2	stress_all	pattgen_stress_all	4.000s	211.352us	1	1	100.00
V2	alert_test	pattgen_alert_test	3.000s	41.517us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	60.855us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	140.234us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	140.234us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	5.000s	15.661us	1	1	100.00
		pattgen_csr_rw	3.000s	67.081us	1	1	100.00
		pattgen_csr_aliasing	4.000s	76.475us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	34.716us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	5.000s	15.661us	1	1	100.00
		pattgen_csr_rw	3.000s	67.081us	1	1	100.00
		pattgen_csr_aliasing	4.000s	76.475us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	34.716us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	1.560ms	1	1	100.00
		pattgen_sec_cm	4.000s	133.081us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	1.560ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	47.000s	30.319ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	132.316us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.65350652741371867975202307265730365100741681579155071085883174085894861362231
      Line 215, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11325142925 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 11325159303 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 11325159303 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/10
        UVM_INFO @ 11325659306 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]