ROM_CTRL/32KB Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.950s 139.143us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.230s 554.178us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.300s 246.924us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.510s 1.277ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.530s 1.800ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 613.236us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.300s 246.924us 1 1 100.00
rom_ctrl_csr_aliasing 4.530s 1.800ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.110s 174.636us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.020s 208.838us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.630s 599.220us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.080s 417.646us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 10.490s 315.670us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.530s 168.237us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.020s 207.241us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.020s 207.241us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.230s 554.178us 1 1 100.00
rom_ctrl_csr_rw 5.300s 246.924us 1 1 100.00
rom_ctrl_csr_aliasing 4.530s 1.800ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.050s 214.455us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.230s 554.178us 1 1 100.00
rom_ctrl_csr_rw 5.300s 246.924us 1 1 100.00
rom_ctrl_csr_aliasing 4.530s 1.800ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.050s 214.455us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 18.290s 5.445ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.549m 858.555us 1 1 100.00
rom_ctrl_tl_intg_err 24.430s 222.590us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.549m 858.555us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.549m 858.555us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.549m 858.555us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.549m 858.555us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.950s 139.143us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.950s 139.143us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.950s 139.143us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 24.430s 222.590us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
rom_ctrl_kmac_err_chk 10.490s 315.670us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.522m 10.300ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 18.290s 5.445ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.549m 858.555us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.902m 3.723ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00